Semiconductor device

ABSTRACT

Provided is a semiconductor device having improved performance. The semiconductor device includes the memory cells of a flash memory. Each of the memory cells includes a capacitor element for writing/erasing data having a gate electrode formed of a part of a floating gate electrode, and a MISFET for reading data having a gate electrode formed of another part of the floating gate electrode. The capacitor element for writing/erasing data has a p-type semiconductor region and an n-type semiconductor region which have opposite conductivity types. The length of the floating gate electrode in a gate length direction in the capacitor element for writing/erasing data is smaller than the length of the floating gate electrode in the gate length direction in the MISFET for reading data.

CROSS-REFERENCE TO RELATED APPLICATION

The disclosure of Japanese Patent Application No. 2013-272503 filed onDec. 27, 2013 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a semiconductor device and can be usedappropriately for, e.g., a semiconductor device having a semiconductorelement formed in a semiconductor substrate.

Some of semiconductor devices have nonvolatile memories each forstoring, e.g., information used during recovery from a defect or duringtrimming such as LCD (Liquid Crystal Display) image adjustment orrelatively-small-capacity information such as the manufacturing numberof the semiconductor in the inside thereof. Examples of such nonvolatilememories include a nonvolatile memory formed of a conductor film ofpolysilicon or the like.

Japanese Unexamined Patent Publication No. 2007-110073 (PatentDocument 1) discloses such a nonvolatile memory formed of a conductorfilm of polysilicon or the like. In the nonvolatile memory disclosed inPatent Document 1, a floating gate electrode made of the conductor filmof polysilicon or the like is formed over the main surface of asemiconductor substrate via a gate insulating film. In the non-volatilememory disclosed in Patent Document 1, at respective positions where thefloating gate electrode overlaps a plurality of active regions formed inthe main surface of the semiconductor substrate, a capacitor portion forwriting/erasing data, a transistor for reading data, and a capacitorportion are placed. In the non-volatile memory disclosed in PatentDocument 1, in the capacitor element for writing/erasing data, data isrewritten using an FN (Fowler-Nordheim) tunnel current.

Japanese Unexamined Patent Publication No. 2011-9454 (Patent Document 2)discloses such a nonvolatile memory formed of a conductor film ofpolysilicon or the like. In the nonvolatile memory disclosed in PatentDocument 2, over the main surface of a semiconductor substrate, afloating gate electrode made of a conductor film of polysilicon or thelike is formed via a gate insulating film. In the nonvolatile memorydisclosed in Patent Document 2, a charge storage portion having thefloating gate electrode and a semiconductor region are formed.

In Non-Patent Document 1, a MTP (Multiple Time Programmable) nonvolatilememory is disclosed. In the nonvolatile memory disclosed in Non-Patentdocument 1, over the main surface of a semiconductor substrate, afloating gate electrode made of a conductor film of polysilicon or thelike is formed via a gate insulating film. In the nonvolatile memorydisclosed in Non-Patent document 1, at respective positions where thefloating gate electrode overlaps two active regions formed in the mainsurface of the semiconductor substrate, a control gate capacitor elementand a tunnel gate capacitor element are placed.

RELATED ART DOCUMENTS Patent Documents [Patent Document 1]

-   Japanese Unexamined Patent Publication No. 2007-110073 [Patent    Document 2]-   Japanese Unexamined Patent Publication No. 2011-9454

Non-Patent Document [Non-Patent Document 1]

-   IEEE Trans. Electron Devices, Vol. 60, pp. 1892-1897, 2013.

SUMMARY

In a semiconductor device including such a nonvolatile memory using afloating gate electrode made of a conductor film of polysilicon or thelike, the floating gate electrode can be formed in the same step offorming the gate electrode of a MISFET (Metal Insulator SemiconductorField Effect Transistor) as a type of field effect transistor (FET).This can facilitate the manufacturing process of the semiconductordevice, improve the manufacturing yield of the semiconductor device, andimprove the reliability of the semiconductor device.

However, in a semiconductor device including such a nonvolatile memoryusing a floating gate electrode made of a conductor film of polysiliconor the like, the area occupied by each of memory cells is relativelylarge. Accordingly, the capacity of the nonvolatile memory cannot easilybe increased and the performance of the semiconductor device cannot beimproved.

Other problems and novel features of the present invention will becomeapparent from a statement in the present specification and theaccompanying drawings.

According to an embodiment, a semiconductor device includes a memorycell of a nonvolatile memory. The memory cell includes an element forwriting/erasing data having a gate electrode formed of a part of afloating gate electrode, and a field effect transistor for reading datahaving a gate electrode formed of another part of the floating gateelectrode. The element for writing/erasing data have a pair ofsemiconductor regions having opposite conductivity types. A length ofthe floating gate electrode in a gate length direction in the elementfor writing/erasing data is smaller than a length of the floating gateelectrode in the gate length direction in the field effect transistorfor reading data.

According to the embodiment, the performance of the semiconductor devicecan be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a main-portion circuit diagram of a flash memory in asemiconductor device in Embodiment 1;

FIG. 2 is a plan view of each of memory cells in the semiconductordevice in Embodiment 1;

FIG. 3 is a cross-sectional view of the memory cell in the semiconductordevice in Embodiment 1;

FIG. 4 is a cross-sectional view showing an example of voltages appliedto the individual portions of the memory cell in a data write operationin the flash memory in Embodiment 1;

FIG. 5 is a cross-sectional view showing an example of voltages appliedto the individual portions of the memory cell in a data erase operationin the flash memory in Embodiment 1;

FIG. 6 is a cross-sectional view showing an example of voltages appliedto the individual portions of the memory cell in a data read operationin the flash memory in Embodiment 1;

FIG. 7 is a main-portion cross-sectional view of the semiconductordevice in Embodiment 1 during a manufacturing process thereof;

FIG. 8 is a main-portion cross-sectional view of the semiconductordevice in Embodiment 1 during the manufacturing process thereof;

FIG. 9 is a main-portion cross-sectional view of the semiconductordevice in Embodiment 1 during the manufacturing process thereof;

FIG. 10 is a main-portion cross-sectional view of the semiconductordevice in Embodiment 1 during the manufacturing process thereof;

FIG. 11 is a main-portion cross-sectional view of the semiconductordevice in Embodiment 1 during the manufacturing process thereof;

FIG. 12 is a main-portion cross-sectional view of the semiconductordevice in Embodiment 1 during the manufacturing process thereof;

FIG. 13 is a main-portion circuit diagram of a flash memory in asemiconductor device in Comparative Example 1;

FIG. 14 is a plan view of each of memory cells in the semiconductordevice in Comparative Example 1;

FIG. 15 is a cross-sectional view of the memory cell in thesemiconductor device in Comparative Example 1;

FIG. 16 is a main-portion circuit diagram of a flash memory in asemiconductor device in Embodiment 2;

FIG. 17 is a plan view of each of memory cells in the semiconductordevice in Embodiment 2;

FIG. 18 is a cross-sectional view of the memory cell in thesemiconductor device in Embodiment 2;

FIG. 19 is a cross-sectional view showing an example of voltages appliedto the individual portions of the memory cell in a data write operationin the flash memory in Embodiment 2;

FIG. 20 is a graph showing a coupling ratio when the ratio of thecapacitance value of an assist capacitor element to the capacitancevalue of a MISFET for reading data is varied;

FIG. 21 is a cross-sectional view showing an example of voltages appliedto the individual portions of the memory cell in a data erase operationin the flash memory in Embodiment 2; and

FIG. 22 is a cross-sectional view showing an example of voltages appliedto the individual portions of the memory cell in a data read operationin the flash memory in Embodiment 2.

DETAILED DESCRIPTION

In the following embodiments, if necessary for the sake of convenience,each of the embodiments will be described by being divided into aplurality of sections or embodiments. However, they are by no meansirrelevant to each other unless particularly explicitly describedotherwise, and one of the sections or embodiments is modifications,details, supplementary explanation, and so forth of part or the whole ofthe others.

Also in the following embodiments, when the number and the like(including the number, numerical value, amount, range, and the like) ofelements are mentioned, they are not limited to specific numbers unlessparticularly explicitly described otherwise or unless they are obviouslylimited to the specific numbers. The number and the like of the elementsmay be not less than or not more than the specific numbers.

Also, in the following embodiments, it goes without saying that thecomponents thereof (including also elements, steps, and the like) arenot necessarily indispensable unless particularly explicitly describedotherwise or unless the components are considered to be obviouslyindispensable in principle. Likewise, if the shapes, positionalrelationships, and the like of the components and the like are mentionedin the following embodiments, the shapes, positional relationships, andthe like are assumed to include those substantially proximate or similarthereto and the like unless particularly explicitly described otherwiseor unless it can be considered that they obviously do not in principle.The same shall apply to the foregoing numerical value and range.

Hereinbelow, the representative embodiments will be described in detailon the basis of the drawings. Note that, throughout all the drawings forillustrating the embodiments, members having the same functions aredesignated by the same reference numerals, and the repeated descriptionthereof is omitted. Also, in the following embodiments, a description ofthe same or like parts will not be repeated in principle unlessparticularly necessary.

In the drawings used in the embodiments, hatching may be omitted even ina cross-sectional view for improved clarity of illustration, while evena plan view may be hatched for improved clarity of illustration.

Embodiment 1

First, a description will be given of a semiconductor device inEmbodiment 1. In the semiconductor device in Embodiment 1, a maincircuit and a flash memory as a nonvolatile memory which storesrelatively-small-capacity intended information related to the maincircuit are formed in the same semiconductor chip.

Examples of the foregoing main circuit include a memory circuit such asa DRAM (Dynamic Random Access Memory) or an SRAM (Static Random AccessMemory), a logic circuit such as a CPU (Central Processing Unit) or anMPU (Micro Processing Unit), and a mixed-signal circuit in which such amemory circuit and such a logic circuit are embedded. Examples of theforegoing main circuit also include an LCD (Liquid Crystal Device)driver circuit. Examples of the foregoing intended information includesinformation on the address in a semiconductor chip where an element usedin trimming is placed, information on the address where a memory cell oran LCD element used in recovering the memory circuit or LCD drivercircuit is placed, trimming tap information for an adjustment voltageused in adjusting an LCD image, and the manufacturing number of asemiconductor device.

<Circuit Configuration of Semiconductor Device>

A description will be given first of a circuit configuration of thesemiconductor device in Embodiment 1. FIG. 1 is a main-portion circuitdiagram of the flash memory in the semiconductor device in Embodiment 1.It is assumed that, in the plane shown in FIG. 1, the two directionscrossing to each other, or preferably orthogonal to each other, are anX-axis direction and a Y-axis direction.

The flash memory in the semiconductor device in Embodiment 1 has amemory cell array MR1. In the memory cell array MR1, a plurality of bitlines WBL for writing/erasing data each extending in the Y-axisdirection are arranged along the X-axis direction crossing, orpreferably orthogonal to, the Y-axis direction. Also, in the memory cellarray MR1, a plurality of bit lines RBL for reading data each extendingin the Y-axis direction are arranged along the X-axis direction. Also,in the memory cell array MR1, a plurality of control gate lines CG1 andCG0 each extending along the X-axis direction and crossing the bit linesWBL and RBL are arranged along the Y-axis direction. Also, in the memorycell array MR1, a plurality of selection lines GS each extending alongthe X-axis direction and crossing the bit lines WBL and RBL are arrangedalong the Y-axis direction.

Note that each of the plurality of control gate lines CG1 is used alsoas a source line SL. Each of the plurality of control gate lines CG0 isused also as a p-type well HPW2 which will be described using FIGS. 2and 3 described later. The control gate lines CG1 and CG0 will be simplyreferred to also as word lines.

Each of the bit lines WBL for writing/erasing data is electricallycoupled to an inverter circuit for inputting data placed in a peripheralcircuit region as a region outside the region where the memory cellarray MR1 is formed, though the illustration thereof is omitted. Each ofthe bit lines RBL for reading data is electrically coupled to a senseamplifier circuit placed in the peripheral circuit region.

In the vicinity of the points of intersection between the bit lines WBLand RBL and the control gate lines CG1 and the selection lines GS,memory cells MC1 each corresponding to one bit are electrically coupledthereto. FIG. 1 illustrates an exemplary case where one bit is formed ofone of the memory cells MC1.

Each of the memory cells MC1 includes a capacitor element CWE forwriting/erasing data, a MISFET QR for reading data, and a selectionMISFET QS. Note that, as described above, a MISFET is a type of FET. Theselection MISFET QS is a selection MISFET for selecting the memory cellMC1

One of the electrodes of the capacitor element CWE for writing/erasingdata is electrically coupled to one of the bit lines WBL forwriting/erasing data. The other electrode of the capacitor element CWEfor writing/erasing data is formed of a part of a floating gateelectrode FG, which will be described using FIGS. 2 and 3 describedlater. The gate electrode of the MISFET QR for reading data is formed ofanother part of the floating gate electrode FG. Consequently, the otherelectrode of the capacitor element CWE for writing/erasing data iselectrically coupled to the gate electrode of the MISFET QR for readingdata. On the other hand, the drain of the MISFET QR for reading data iselectrically coupled to one of the bit lines RBL for reading data viathe selection MISFET QS. The source of the MISFET QR for reading data iselectrically coupled to the control gate line CG1, which is used also asthe source line SL. The gate electrode of the selection MISFET iselectrically coupled to one of the selection lines GS.

<Configuration of Memory Cell>

Next, a description will be given of a configuration of each of thememory cells of the flash memory in the semiconductor device inEmbodiment 1. FIG. 2 is a plan view of each of the memory cells in thesemiconductor device in Embodiment 1. FIG. 3 is a cross-sectional viewof the memory cell in the semiconductor device in Embodiment 1. Each ofFIGS. 2 and 3 shows the memory cell corresponding to one bit. FIG. 3 isa cross-sectional view along the line A-A in FIG. 2.

It is assumed that, in the plane shown in FIG. 2, the two directionscrossing each other, or preferably orthogonal to each other, are theX-axis direction and the Y-axis direction. FIG. 2 shows the memory cellin a see-through state where conductor portions 7 a to 7 f, aninsulating film 6, a cap insulating film 14, silicide layers 5 a,sidewalls SW, and isolation portions TI have been removed. FIG. 2 showsonly the outer periphery of the cap insulating film 14. For improvedclarity of illustration, FIG. 2 is partly hatched.

As described above, each of the memory cells MC1 of the flash memory inthe semiconductor device in Embodiment 1 includes the floating gateelectrode FG, the capacitor element CWE for writing/erasing data, andthe MISFET QR for reading data.

A semiconductor substrate (hereinafter referred to simply as substrate)1S forming the semiconductor device is made of, e.g., a silicon (Si)single crystal having a p-type conductivity type. In the substrate 1S,an n-type embedded well DNW having the conductivity type opposite to thep-type is formed to extend from the main surface of the substrate 1S toa predetermined depth. That is, in the main surface of the substrate 1S,the n-type embedded well DNW is formed.

In the main surface of the substrate 1S, the isolation portions TI areplaced. The isolation portions TI define active regions L1, L2, L3, andL4. The isolation portions TI are trench-type isolation portions eachreferred to as a so-called SGI (Shallow Groove Isolation) or STI(Shallow Trench Isolation) formed by, e.g., embedding an insulating filmmade of silicon dioxide (SiO₂) or the like in the shallow trenchesformed in the main surface of the substrate 1S.

In the n-type embedded well DNW, p-type wells HPW1 and HPW2 and ann-type well HNW are formed. The p-type wells HPW1 and HPW2 are locatedso as to be included in the n-type embedded well DNW, while beingelectrically isolated from each other by the n-type embedded well DNWand the n-type well HNW. The p-type well HPW2 is located so as to extendalong the p-type well HPW1.

Each of the p-type wells HPW1 and HPW2 contains a p-type impurity suchas, e.g., boron (B). In a part of the layer located over the p-type wellHPW2, a p⁺-type semiconductor region 4 a as the active region L3described above is formed. The p⁺-type semiconductor region 4 a containsthe same impurity as contained in the p-type well HPW2, but the impurityconcentration thereof in the p⁺-type semiconductor region 4 a is sethigher than the impurity concentration thereof in the p-type well HPW2.The p⁺-type semiconductor region 4 a is electrically coupled to theconductor portion 7 a in one of contact holes CT formed in an insulatingfilm 6 over the main surface of the substrate 1S. In parts of the topsurface layer of the p⁺-type semiconductor region 4 a which is incontact with the conductor portion 7 a, silicide layers 5 a each madeof, e.g., cobalt silicide (CoSi_(x)) or the like may also be formed.

The n-type well HNW contains an n-type impurity such as, e.g.,phosphorus (P) or arsenic (As). In parts of the layer located over then-type well HNW, an n⁺-type semiconductor region 8 a are formed. Then⁺-type semiconductor region 8 a contains the same impurity as containedin the n-type well HNW, but the impurity concentration thereof in then⁺-type semiconductor region 8 a is set higher than the impurityconcentration thereof in the n-type well HNW.

The n⁺-type semiconductor region 8 a described above is electricallycoupled to the conductor portions 7 b in the contact holes CT formed inthe insulating film 6. In parts of the top surface layer of the n⁺-typesemiconductor region 8 a which is in contact with the conductor portions7 b, the silicide layers 5 a may also be formed.

FIGS. 2 and 3 show an example in which the n-type well HNW is in contactwith the p-type wells HPW1 and HPW2. However, the n-type well HNW mayalso be apart from the p-type well HPW1 or HPW2 so as not to come incontact with the p-type well HPW1 or HPW2. In other words, between then-type well HNW and the p-type well HPW1 or HPW2, parts of the n-typeembedded well DNW may also be interposed.

The floating gate electrode FG is a portion in which chargescontributing to the storage of information are stored. The floating gateelectrode FG is made of a conductor film of, e.g., low-resistancepolysilicon or the like and formed in an electrically floating state,i.e., in a state insulated from another conductor. As shown in FIG. 2,the floating gate electrode FG is formed in a state extending along theY-axis direction so as to two-dimensionally overlap the p-type wellsHPW1 and HPW2. Note that the memory cell MC1 is also placed so as totwo-dimensionally overlap the p-type wells HPW1 and HPW2.

At the position where the floating gate electrode FG two-dimensionallyoverlaps the active region L1 of the p-type well HPW1, the capacitorelement CWE for writing/erasing data is placed. The capacitor elementCWE for writing/erasing data includes a capacitor electrode FGC1, acapacitor insulating film 10 a, a p-type semiconductor region 11, ann-type semiconductor region 12, and the p-type well HPW1.

The capacitor electrode FGC1 is formed of a part of the floating gateelectrode FG. In other words, the capacitor electrode FGC1 is theportion of the floating gate electrode FG which is formed at a positionwhere the floating gate electrode FG two-dimensionally overlaps theactive region L1 of the p-type well HPW1. The capacitor electrode FGC1is also a portion forming the upper electrode of the capacitor elementCWE.

The capacitor insulating film 10 a is made of, e.g., silicon dioxide(SiO₂) and formed between the capacitor electrode FGC1 and the substrate1S, i.e., the p-type well HPW1. The capacitor insulating film 10 a has athickness of, e.g., not less than 10 nm and not more than 20 nm. Notethat, in the capacitor electrode CWE, in rewriting data, electrons orholes are injected from the p-type well HPW1 into the capacitorelectrode FGC1 via the capacitor insulating film 10 a or electrons orholes are released from the capacitor element FGC1 into the p-type wellHPW1 via the capacitor insulating film 10 a. Accordingly, the capacitorinsulating film 10 a has a small thickness which is set to, e.g., about12 nm. The reason for setting the thickness of the capacitor insulatingfilm 10 a to a value of not less than 10 nm is that, if the thickness ofthe capacitor insulating film 10 a is smaller than the value, thereliability of the capacitor insulating film 10 a cannot be ensured. Thereason for setting the thickness of the capacitor insulating film 10 ato a value of not more than 20 nm is that, if the thickness of thecapacitor insulating film 10 a is larger than the value, it is difficultto allow electrons or holes to pass through the capacitor insulatingfilm 10 a and rewriting of data cannot easily be performed.

The p-type semiconductor region 11 and the n-type semiconductor region12 are formed at respective positions in the p-type well HPW1 betweenwhich the capacitor electrode FGC1 is two-dimensionally interposed byself-alignment with the capacitor electrode FGC1.

The p-type semiconductor region 11 includes a channel-side p⁻-typesemiconductor region 11 a, and a p⁺-type semiconductor region 11 bcoupled to the p⁻-type semiconductor region 11 a. Each of the p⁻-typesemiconductor region 11 a and the p⁺-type semiconductor region 11 bcontains a p-type impurity such as, e.g., boron (B). However, theimpurity concentration thereof in the p⁺-type semiconductor region 11 bis set higher than the impurity concentration thereof in the p⁻-typesemiconductor region 11 a. The p-type semiconductor region 11 iselectrically coupled to the conductor portion 7 c in one of the contactholes CT formed in the insulating film 6. The conductor portion 7 c iselectrically coupled to the bit line WBL for writing/erasing data. In apart of the top surface layer of the p⁺-type semiconductor region 11 bwhich is in contact with the conductor portion 7 c, the silicide layer 5a may also be formed.

The p-type semiconductor region 11 is electrically coupled to the p-typewell HPW1. Accordingly, the p-type well HPW1 is the portion forming thelower electrode of the capacitor element CWE.

The n-type semiconductor region 12 includes a channel-side n⁻-typesemiconductor region 12 a, and an n⁺-type semiconductor region 12 bcoupled to the n⁻-type semiconductor region 12 a. Each of the n⁻-typesemiconductor region 12 a and the n⁺-type semiconductor region 12 bcontains an n-type impurity such as, e.g., phosphorus (P) or arsenic.However, the impurity concentration thereof in the n⁺-type semiconductorregion 12 b is set higher than the impurity concentration thereof in then⁻-type semiconductor region 12 a. The n-type semiconductor region 12 iselectrically coupled to the conductor portion 7 c in one of the contactholes CT formed in the insulating film 6. The conductor portion 7 c iselectrically coupled to the bit line WBL for writing/erasing data. In apart of the top surface layer of the n⁺-type semiconductor region 12 bwhich is in contact with the conductor portion 7 c, the silicide layer 5a may also be formed.

Thus, at the positions in the p-type well HPW1 between which thecapacitor electrode FGC1 is two-dimensionally interposed, the p-typesemiconductor region 11 and the n-type semiconductor region 12 which area pair of semiconductor regions having opposite conductivity types areformed. As a result, even when a voltage having either the positivepolarity or the negative polarity is applied to the bit line WBL forwriting/erasing data, no depletion layer is formed in a layer locatedover the portion where the capacitor electrode FGC1 two-dimensionallyoverlaps the active region L1 of the p-type well HPW1, i.e., the regioncorresponding to a channel. Therefore, it is possible to apply a voltagehaving either the positive polarity or the negative polarity to theportion of the p-type well HPW1 which faces the capacitor electrodeFGC1.

On the other hand, at the position where the floating gate electrode FGtwo-dimensionally overlaps the active region L2 of the p-type well HPW2,the MISFET QR for reading data is placed. The MISFET QR for reading dataincludes a gate electrode FGR, a gate insulating film 10 b, and a pairof n-type semiconductor regions 13. The channel of the MISFET QR forreading data is formed in a layer located over the portion where thegate electrode FGR two-dimensionally overlaps the active region L2 ofthe p-type well HPW2.

The gate electrode FGR is formed of a part of the floating gateelectrode FG. In other words, the gate electrode FGR is the portion ofthe floating gate electrode FG which is formed at a position where thefloating gate electrode FG two-dimensionally overlaps the active regionL2 of the p-type well HPW2. In Embodiment 1, the MISFET QR for readingdata functions also as a capacitor element C. Accordingly, the gateelectrode FGR is also the portion forming the upper electrode of thecapacitor element C.

The gate insulating film 10 b is made of, e.g., silicon dioxide (SiO₂)and formed between the gate electrode FGR and the substrate 1S, i.e.,the p-type well HPW2. The gate insulating film 10 b has a thickness of,e.g., about 12 nm, which is similar to the thickness of the capacitorinsulating film 10 a.

The pair of n-type semiconductor regions 13 of the MISFET QR for readingdata are formed at respective positions in the p-type well HPW2 betweenwhich the gate electrode FGR is two-dimensionally interposed byself-alignment with the gate electrode FGR.

Each of the pair of n-type semiconductor regions 13 of the MISFET QR forreading data includes a channel-side n⁻-type semiconductor region 13 a,and an n⁺-type semiconductor region 13 b coupled to the n⁻-typesemiconductor region 13 a, similarly to the n-type semiconductor region12 described above. Each of the n⁻-type semiconductor region 13 a andthe n⁺-type semiconductor region 13 b contains an n-type impurity suchas, e.g., phosphorus (P) or arsenic (As). However, the impurityconcentration thereof in the n⁺-type semiconductor region 13 b is sethigher than the impurity concentration thereof in the n⁻-typesemiconductor region 13 a.

The pair of n-type semiconductor regions 13 of the MISFET QR for readingdata are referred to as n-type semiconductor regions 13 c and 13 d. Atthis time, the n-type semiconductor region 13 c as one of the pair ofn-type semiconductor regions 13 of the MISFET QR for reading data iselectrically coupled to the conductor portion 7 d in one of the contactholes CT formed in the insulating film 6. The conductor portion 7 d iselectrically coupled to the control gate line CG1, which is used also asthe source line SL. Over a part of the top surface layer of the n⁺-typesemiconductor region 13 b which is in contact with the conductor portion7 d, the silicide layer 5 a may also be formed. On the other hand, then-type semiconductor region 13 d as the other of the pair of n-typesemiconductor regions 13 of the MISFET QR for reading data is shared asone of the pair of n-type semiconductor regions 13 of the selectionMISFET QS described later by the MISFET QR for reading data and theselection MISFET QS.

As described above, the p-type well HPW2 is electrically coupled to then⁺-type semiconductor region 8 a. Accordingly, the p-type well HPW2 isthe portion forming the lower electrode of the capacitor element C inthe MISFET QR for reading data. That is, the p-type well HPW2 functionsas the second control gate line CG0 of the memory cell.

The selection MISFET QS includes a gate electrode FGS, a gate insulatingfilm 10 c, and the pair of source/drain n-type semiconductor regions 13.The channel of the selection MISFET QS is formed in a layer located overthe portion where the gate electrode FGS two-dimensionally overlaps theactive region L2 of the p-type well HPW2.

The gate electrode FGS is made of a conductor film of, e.g.,low-resistance polysilicon or the like. The gate electrode FGS is placedso as to extend in the Y-axis direction and two-dimensionally overlapthe portion of the p-type well HPW2 opposite to the gate electrode FGRrelative to the n-type semiconductor region 13 d interposed therebetweenand electrically isolated from the floating gate electrode FG. The gateelectrode FGS is electrically coupled to the conductor portion 7 e inone of the contact holes CT formed in the insulating film 6. Theconductor portion 7 e is electrically coupled to the selection line GS.

The gate insulating film 10 c is made of, e.g., silicon dioxide (SiO₂)and formed between the gate electrode FGS and the substrate 1S, i.e.,the p-type well HPW2. The gate insulating film 10 c has a thickness of,e.g., about 12 nm, which is similar to the thickness of the capacitorinsulating film 10 a.

Each of the pair of n-type semiconductor regions 13 of the selectionMISFET QS is similar to each of the n-type semiconductor regions 13 ofthe MISFET QR for reading data. The pair of n-type semiconductor regions13 are formed at respective positions in the p-type well HPW2 betweenwhich the gate electrode FGS is interposed. As described above, then-type semiconductor region 13 d as one of the pair of n-typesemiconductor regions 13 of the selection MISFET QS is shared by theMISFET QR for reading data and the selection MISFET QS. On the otherhand, the n-type semiconductor region 13 e as the other of the pair ofn-type semiconductor regions 13 of the selection MISFET Q iselectrically coupled to the conductor portion 7 f in one of the contactholes CT formed in the insulating film 6. The conductor portion 7 f iselectrically coupled to the bit line RBL for reading data. In a part ofthe top surface layer of the n⁺-type semiconductor region 12 b which isin contact with the conductor portion 7 f, the silicide layer 5 a mayalso be formed.

Over the side surfaces of the floating gate electrode FG, i.e., over therespective side surfaces of the capacitor electrode FGC1 and the gateelectrode FGR and over the side surfaces of the gate electrode FGS, thesidewalls SW each made of, e.g., silicon dioxide (SiO₂) are formed. Overthe upper surface of the floating gate electrode FG, i.e., over therespective upper surfaces of the capacitor electrode FGC1 and the gateelectrode FGR, over the surfaces of the side walls SW formed over therespective side surface of the capacitor electrode FGC1 and the gateelectrode FGR, and over the main surface of the portion of the substrate1S located therearound, the cap insulating film 14 is formed.

The cap insulating film 14 is made of, e.g., silicon dioxide (SiO₂) andformed between the floating gate electrode FG and an insulating film 6 amade of silicon nitride (Si₃N₄) and described later so as to preventdirect contact between the insulating film 6 a and the upper surface ofthe floating gate electrode FG. For example, when the insulating film 6a made of silicon nitride is deposited by a plasma chemical vapordeposition (CVD) method or the like, a portion in which the compositionratio of silicon is high, i.e., a silicon-rich portion is likely to beformed in the insulating film 6 a. In such a case, charges in thefloating gate electrode FG may flow toward the substrate 1S through thesilicon-rich portion of the insulating film 6 a to be released throughthe conductor portion and possibly degrade the data retention propertyof the flash memory. However, by forming the cap insulating film 14between the floating gate electrode FG and the insulating film 6 a, itis possible to prevent or inhibit such a charge release as describedabove and thus improve the data retention property of the flash memory.

The silicide layers 5 a are formed after the formation of the capinsulating film 14. Consequently, the silicide layers 5 a are formed inthe main surface of the substrate 1S, i.e., in the top surface layers ofthe p⁺-type semiconductor region 11 b and the n⁺-type semiconductorregions 12 b and 13 b, but are not formed in the upper surface of thefloating gate electrode FG.

Over the main surface of the substrate 1S including the top surface ofthe cap insulating film 14, the insulating film 6 is formed. Over theupper surface of the floating gate electrode FG, i.e., over therespective upper surfaces of the capacitor electrode FGC1 and the gateelectrode FGR, over the surfaces of the sidewalls SW formed over therespective side surfaces of the capacitor electrode FGC1 and the gateelectrode FGR, and over the main surface of the portion of the substrate1S located therearound, the insulating film 6 is formed via the capinsulating film 14. The insulating film 6 includes the insulating film 6a, and an insulating film 6 b deposited over the insulating film 6 a.The lower-layer insulating film 6 a is made of, e.g., silicon nitride(Si₃N₄). The upper-layer insulating film 6 b is made of, e.g., silicondioxide (SiO₂).

In Embodiment 1, a length LNwe of the capacitor electrode FGC1 of thecapacitor element CWE for writing/erasing data in the X-axis directionis smaller than a length LNr of the gate electrode FGR of the MISFET QRfor reading data in the X-axis direction. This allows the capacitancevalue of the capacitor element CWE for writing/erasing data to be setsmaller than the capacitance value of the capacitor element C servingalso as the MISFET QR for reading data. As will be explained in anexample of a data write operation in the flash memory described later,by setting the capacitance value of the capacitor element CWE smallerthan the capacitance value of the capacitor element C, a coupling ratioin writing data and in erasing data can be increased. As a result, datacan easily be written/erased.

In Comparative Example 1 described later, such a portion is provided inwhich the length of a capacitor electrode FGC100 of a capacitor elementC100 (see FIG. 14 described later), i.e., the length of the floatinggate electrode FG in the X-axis direction is larger than the length ofthe gate electrode FGR of the MISFET QR for reading data in the X-axisdirection. However, in Embodiment 1, such a portion is not provided. Insuch a case, it is preferable that the gate electrode FGR of the MISFETQR for reading data is the portion of the floating gate electrode FGwhere the length of the floating gate electrode FG in the X-axisdirection is largest.

It is also preferable that a length LNs of the gate electrode FGS of theselection MISFET QS in the X-axis direction is larger than the lengthLNr of the gate electrode FGR in the X-axis direction. This can preventor inhibit a punch-through in the selection MISFET QS and reduce aleakage current in an OFF state, i.e., OFF leakage current. On the otherhand, in the MISFET QR for reading data, it is less necessary to preventor inhibit a punch-through than in the selection MISFET QS. Accordingly,the length LNr of the gate electrode FGR in the X-axis direction mayalso be smaller than the length LNs of the gate electrode FGS in theX-axis direction.

It is also preferable that, at any position between the position wherethe floating gate electrode FG two-dimensionally overlaps the p-typewell HPW1 and the position where the floating gate electrode FGtwo-dimensionally overlaps the p-type well HPW2, the length of thefloating gate electrode FG in the X-axis direction is not less than thelength LNwe of the capacitor electrode FGC1 in the X-axis direction.That is, at any position between the capacitor electrode FGC1 and thegate electrode FGR, the length of the floating gate electrode FG in theX-axis direction is not smaller than the length LNr of the capacitorelectrode FGC1 in the X-axis direction so that the floating gateelectrode FG does not have a constricted shape. This can reduce theelectric resistance of the portion of the floating gate electrode FGwhich is located between the capacitor electrode FGC1 and the gateelectrode FGR. Therefore, it is possible to prevent or inhibit a lossresulting from the occurrence of a voltage drop between the capacitorelectrode FGC1 and the gate electrode FGR or the like.

It is also preferable that a width WDwe of the portion of the capacitorelectrode FGC1 which is interposed between the p-type semiconductorregion 11 and the n-type semiconductor region 12 in the Y-axis directionis smaller than a width WDr of the portion of the gate electrode FGRwhich is interposed between the n-type semiconductor regions 13 c and 13d in the Y-axis direction. As a result, the width WDr of the gateelectrode FGR in the Y-axis direction relatively increases to allow anincrease in the read current flowing in the MISFET QR for reading dataand allow for high-speed reading.

<Example of Data Write Operation>

Next, a description will be given of an example of a data writeoperation in such a flash memory. FIG. 4 is a cross-sectional viewshowing an example of voltages applied to the individual portions of thememory cell in a data write operation in the flash memory inEmbodiment 1. FIG. 4 is a cross-sectional view along the line A-A inFIG. 2.

In writing data, a positive voltage of, e.g., about 8 V is applied toeach of the n-type well and the n-type embedded well DNW through each ofthe conductor portions 7 b to electrically isolate the substrate 1S andthe p-type wells HPW1 and HPW2 from each other. When the substrate 1S isa p-type silicon single crystal substrate, a reverse bias is applied toa pn junction at an interface IF11 which is the interface between theportion of the substrate 1S underlying the portion thereof formed withthe n-type embedded well DNW and the n-type embedded well DNW and shownby the thick line in FIG. 4. In this manner, the substrate 1S and then-type embedded well DNW are electrically isolated from each other. Theelectrical isolation provided between the substrate 1S and the n-typeembedded well DNW provides electrical isolation between the substrate 1Sand the p-type wells HPW1 and HPW2.

Also, a positive voltage of, e.g., about 8 V is applied to each of thep⁺-type semiconductor region 4 a and the p-type well HPW2 through theconductor portion 7 a. At this time, since each of the p⁺-typesemiconductor region 4 a and the p-type well HPW2 is formed of a p-typesemiconductor, as schematically shown by an arrow AW11, the potentialdifference between the p⁺-type semiconductor region 4 a and the p-typewell HPW2 is equal to about 0 V. The arrow AW11 means that the potentialdifference between the starting end and terminating end of the arrow isequal to about 0 V.

Since a forward bias is applied to a pn junction at the interfacebetween the p-type well HPW2 and the n-type well HNW, as schematicallyshown by an arrow AW12, the potential difference between the p-type wellHPW2 and the n-type well HNW is equal to about 0 V. The arrow AW12 meansthat the potential difference between the starting end and terminatingend of the arrow is equal to about 0 V.

Also, a positive voltage of, e.g., about 8 V is applied from the controlgate line CG1 to the n-type semiconductor region 13 c as one of the pairof n-type semiconductor regions 13 of the MISFET QR for reading datathrough the conductor portion 7 d. At this time, as schematically shownby an arrow AW13, the potential difference between the n-typesemiconductor region 13C coupled to the conductor portion 7 d and thep-type well HPW2 is equal to about 0 V. The arrow AW13 means that thepotential difference between the starting end and terminating end of thearrow is equal to about 0 V.

Also, a positive voltage of, e.g., about 8 V is applied from the bitline RBL for reading data to the semiconductor region 13 e as the otherof the pair of n-type semiconductor regions 13 of the selection MISFETQS through the conductor portion 7 f. At this time, as schematicallyshown by an arrow AW14, the potential difference between the n-typesemiconductor region 13 e coupled to the conductor portion 7 f and thep-type well HPW2 is equal to about 0 V. The arrow AW14 means that thepotential difference between the starting end and terminating end of thearrow is equal to about 0 V.

Also, a positive voltage of, e.g., about 8 V is applied from theselection line GS to the gate electrode FGS of the selection MISFET QSthrough the conductor portion 7 e or, alternatively, the gate electrodeFGS is brought into an open state (shown as “Open” in FIG. 4).

On the other hand, a negative voltage of, e.g., about −8 V is appliedfrom each of the bit lines WBL for writing/erasing data to each of thep-type semiconductor region 11 of the capacitor element CWE forwriting/erasing data, the n-type semiconductor region 12 thereof, andthe p-type well HPW1 thereof through each of the conductor portions 7 c.At this time, since each the p-type semiconductor region and the p-typewell HPW1 is formed of a p-type semiconductor, as schematically shown byan arrow AW15, the potential difference between the p-type semiconductorregion 11 and the p-type well HPW1 is equal to about 0 V. The arrow AW15means that the potential difference between the starting end andterminating end of the arrow is equal to about 0 V. Since the potentialdifference between the p-type semiconductor region 11 and the p-typewell HPW1 is equal to about 0 V, as schematically shown by an arrowAW16, the potential difference between the n-type semiconductor region12 and the p-type well HPW1 is also equal to about 0 V. The arrow AW16means that the potential difference between the starting end andterminating end of the arrow is equal to about 0 V.

On the other hand, a reverse bias is applied to a pn junction at aninterface IF12 which is the interface between the p-type well HPW1 andeach of the n-type well HNW and the n-type embedded well DNW and shownby the thick line in FIG. 4 to produce a potential difference of, e.g.,about 16 V.

Thus, to each of the n-type embedded well DNW and the p-type well HPW2forming the lower electrode of the capacitor element C serving also asthe MISFET QR for reading data, a positive voltage of, e.g., about 8 Vis applied. On the other hand, to the p-type well HPW1 forming the lowerelectrode of the capacitor element CWE for writing/erasing data, anegative voltage of, e.g., about −8 V, i.e., voltage having the polarityopposite to the polarity of the voltage applied to the p-type well HPW2is applied via the p-type semiconductor region 11.

By the application of such voltages, the p-type wells HPW1 and HPW2 areindividually controlled. As a result, electrons e⁻ are injected as an FNtunnel current from the entire surface of the channel from the p-typewell HPW1 into the capacitor electrode FGC1 through the capacitorinsulating film 10 a or holes are released as an FN tunnel current fromthe capacitor electrode FGC1. In this manner, data is written.

Note that whether, e.g., electrons or holes are injected or released asan FN tunnel current can be determined on the basis of whether or notthe relationship between, e.g., a voltage V and a current I which flowson the application of the voltage V linearly changes in a graph in whichthe abscissa represents 1/V and the ordinate represents log (I/V²).

In writing data, the capacitor element C serving also as the MISFET QRfor reading data and the capacitor element CWE are coupled in series toeach other via the floating gate electrode FG. It is assumed that acapacitance value CAPr is the capacitance value of the capacitor elementC and a capacitance value CAPwe is the capacitance value of thecapacitor element CWE. It is also assumed that a potential difference Vris the potential difference between the p-type well HPW2 forming thelower electrode of the capacitor element C and the gate electrode FGRforming the upper electrode of the capacitor element C. It is alsoassumed that a potential difference Vwe is the potential differencebetween the p-type well HPW1 forming the lower electrode of thecapacitor element CWE and the capacitor electrode FGC1 forming the upperelectrode of the capacitor element CWE.

At this time, a ratio RC1 given by the following expression (1), i.e.,the ratio of the potential difference Vwe to the total sum of thepotential differences Vr and Vwe is defined as the coupling ratiobetween the capacitor elements C and CWE. As described above, since thecapacitor elements C and CWE are coupled in series to each other via thefloating gate electrode FG, the coupling ratio RC1 is given by thefollowing expression (2). Accordingly, by increasing the ratio of thecapacitance value CAPr to the total sum of the capacitance values CAPrand CAPwe, it is possible to increase the coupling ratio RC1 andincrease the potential difference Vwe in the capacitor element CWE. As aresult, in the capacitor element CWE, electrons are more likely to beinjected as an FN tunnel current into the capacitor electrode FGC1 orholes are more likely to be released as an FN tunnel current from thecapacitor electrode FGC1.

RC1=Vwe/(Vr+Vwe)  (1)

RC1=CAPr/(CAPr+CAPwe)  (2)

Preferably, the capacitor elements C and CWE are designed such that thecapacitance values CAPr and CAPwe satisfy the following expression (3).By satisfying the foregoing expression (3), as shown in Expressions (2)and (1) shown above, it is possible to set the coupling ratio RC1 largerthan 0.5 and set the potential difference Vwe larger than the potentialdifference Vr. As a result, in the capacitor element CWE, electrons aremore likely to be injected as an FN tunnel current into the capacitorelectrode FGC1 or holes are more likely to be released as an FN tunnelcurrent from the capacitor electrode FGC1 than in the capacitor elementC.

CAPr>CAPwe  (3)

As described above, it is assumed that the length LNr is the length ofthe gate electrode FGR in the X-axis direction and the width WDr is thewidth of the gate electrode FGR in the Y-axis direction. It is alsoassumed that the length LNwe is the length of the capacitor electrodeFGC1 in the X-axis direction and the width WDwe is the width of thecapacitor electrode FGC1 in the Y-axis direction. At this time, an areaSr occupied by the gate electrode FGR is given by the followingexpression (4), and an area Swe occupied by the capacitor electrode FGC1is given by the following expression (5). For example, when thecapacitor insulating film 10 a and the gate insulating film 10 b haveequal thicknesses and equal dielectric constants, by satisfying thefollowing expression (6), it is possible to satisfy the foregoingexpression (3). That is, when the area occupied by the portion of thecapacitor electrode FGC1 which is interposed between the p-typesemiconductor region 11 and the n-type semiconductor region 12 issmaller than the area occupied by the portion of the gate electrode FGRwhich is interposed between the n-type semiconductor regions 13 c and 13d, the foregoing expression (3) can be satisfied.

Sr=LNr×WDr  (4)

Swe=LNwe×WDwe  (5)

Sr>Swe  (6)

FIG. 5 is a cross-sectional view showing an example of voltages appliedto the individual portions of the memory cell in a data erase operationin the flash memory in Embodiment 1. FIG. 5 is a cross-sectional viewalong the line A-A in FIG. 2.

In erasing data, a positive voltage of, e.g., about 8 V is applied toeach of the n-type well HNW and the n-type embedded well DNW througheach of the conductor portions 7 b to electrically isolate the substrate1S and the p-type wells HPW1 and HPW2 from each other. When thesubstrate 1S is a p-type silicon single crystal substrate, a reversebias is applied to a pn junction at an interface IF21 which is theinterface between the portion of the substrate 1S underlying the portionthereof formed with the n-type embedded well DNW and the n-type embeddedwell DNW and shown by the thick line in FIG. 5. In this manner, thesubstrate 1S and the n-type embedded well DNW are electrically isolatedfrom each other. The electrical isolation provided between the substrate1S and the n-type embedded well DNW provides electrical isolationbetween the substrate 1S and the p-type wells HPW1 and HPW2.

Also, a negative voltage of, e.g., about −8 V is applied to each of thep⁺-type semiconductor region 4 a and the p-type well HPW2 through theconductor portion 7 a. At this time, since each of the p⁺-typesemiconductor region 4 a and the p-type well HPW2 is formed of a p-typesemiconductor, as schematically shown by an arrow AW21, the potentialdifference between the p⁺-type semiconductor region 4 a and the p-typewell HPW2 is equal to about 0 V. The arrow AW21 means that the potentialdifference between the starting end and terminating end of the arrow isequal to about 0 V.

Also, a negative voltage of, e.g., about −8 V is applied from thecontrol gate line CG1 to the n-type semiconductor region 13 c as one ofthe pair of n-type semiconductor regions 13 of the MISFET QR for readingdata through the conductor portion 7 d. At this time, a forward bias isapplied to a pn junction at the interface between the n-typesemiconductor region 13 c coupled to the conductor portion 7 d and thep-type well HPW2. Consequently, as schematically shown by an arrow AW22,the potential difference between the n-type semiconductor region 13Ccoupled to the conductor portion 7 d and the p-type well HPW2 is equalto about 0 V. The arrow AW22 means that the potential difference betweenthe starting end and terminating end of the arrow is equal to about 0 V.

Also, e.g., 0 V is applied from the bit line RBL for reading data to thesemiconductor region 13 e as the other of the pair of n-typesemiconductor regions 13 of the selection MISFET QS through theconductor portion 7 f. At this time, a reverse bias is applied to a pnjunction at the interface between the n-type semiconductor region 13 ecoupled to the conductor portion 7 f and the p-type well HPW2.Consequently, the potential difference between the n-type semiconductorregion 13 e coupled to the conductor portion 7 f and the p-type wellHPW2 is equal to about 8 V.

Also, a positive voltage of, e.g., about 8 V is applied from theselection line GS to the gate electrode FGS of the selection MISFET QSthrough the conductor portion 7 e or, alternatively, the gate electrodeFGS is brought into the open state (shown as “Open” in FIG. 5).

On the other hand, a positive voltage of, e.g., about 8 V is appliedfrom each of the bit lines WBL for writing/erasing data to each of thep-type semiconductor region 11 of the capacitor element CWE forwriting/erasing data, the n-type semiconductor region 12 thereof, andthe p-type well HPW1 thereof through each of the conductor portions 7 c.At this time, since each of the p-type semiconductor region 11 and thep-type well HPW1 is formed of a p-type semiconductor, as schematicallyshown by an arrow AW23, the potential difference between the p-typesemiconductor region 11 and the p-type well HPW1 is equal to about 0 V.The arrow AW23 means that the potential difference between the startingend and terminating end of the arrow is equal to about 0 V. Since thepotential difference between the p-type semiconductor region 11 and thep-type well HPW1 is equal to about 0 V, as schematically shown by anarrow AW24, the potential difference between the n-type semiconductorregion 12 and the p-type well HPW1 is also equal to about 0 V. The arrowAW24 means that the potential difference between the starting end andterminating end of the arrow is equal to about 0 V.

Since a forward bias is applied to a pn junction at the interfacebetween the p-type well HPW1 and the n-type well HNW, as schematicallyshown by an arrow AW25, the potential difference between the p-type wellHPW1 and the n-type well HNW is equal to about 0 V. The arrow AW25 meansthat the potential difference between the starting end and terminatingend of the arrow is equal to about 0 V.

On the other hand, a reverse bias is applied to a pn junction at aninterface IF22 which is the interface between the p-type well HPW2 andeach of the n-type well HNW and the n-type embedded well DNW and shownby the thick line in FIG. 5 to produce a potential difference of, e.g.,about 16 V.

Thus, to the n-type embedded well DNW, the voltage having the samepolarity as that of the voltage applied to the n-type embedded well DNWin writing data is applied. On the other hand, to the p-type well HPW2forming the lower electrode of the capacitor element C serving also asthe MISFET QR for reading data, a negative voltage of, e.g., about −8 V,i.e., voltage having the polarity opposite to the polarity of thevoltage applied to the n-type embedded well DNW in writing data isapplied. To the p-type well HPW1 forming the lower electrode of thecapacitor element CWE for writing/erasing data, a positive voltage ofabout 8 V, i.e., voltage having the same polarity as that of the voltageapplied to the n-type embedded well DNW in writing data is applied. Notethat, to the p-type well HPW1, the same voltage as the voltage appliedto the n-type embedded well DNW may also be applied.

By the application of such voltages, the p-type wells HPW1 and HPW2 areindividually controlled. As a result, the electrons e⁻ stored in thefloating gate electrode FG serving as the capacitor electrode FGC1 arereleased as an FN tunnel current into the p-type well HPW1 through thecapacitor insulating film 10 a or holes are injected as an FN tunnelcurrent into the capacitor electrode FGC1. In this manner, data iserased.

The coupling ratio in erasing data is the same as the coupling ratio RC1in writing data, i.e., the coupling ratio RC1 shown in the foregoingexpression (2). Accordingly, in erasing data also, in the same manner asin writing data, by increasing the ratio of the capacitance value CAPrto the total sum of the capacitance values CPr and CAPwe, it is possibleto increase the coupling ratio RC1 shown in the foregoing expression (2)and increase the potential difference Vwe in the capacitor element CWE.As a result, in the capacitor element CWE, electrons are more likely tobe released as an FN tunnel current from the capacitor electrode FGC1 orholes are more likely to be injected as an FN tunnel current into thecapacitor electrode EGC1.

Preferably, by satisfying the foregoing expression (3), the couplingratio RC1 can be set larger than 0.5 and the potential difference Vwecan be set larger than the potential difference Vr. As a result, in thecapacitor element CWE, electrons are more likely to be released as an FNtunnel current from the capacitor electrode FGC1 or holes are morelikely to be injected as an FN tunnel current into the capacitorelectrode FGC1 than in the capacitor element C.

FIG. 6 is a cross-sectional view showing an example of voltages appliedto the individual portions of the memory cell in a data read operationin the flash memory in Embodiment 1. FIG. 6 is a cross-sectional viewalong the line A-A in FIG. 2.

In reading data, a voltage of, e.g., about 3 V as a power supply voltageVcc is applied to each of to the n-type well HNW and the n-type embeddedwell DNW to electrically isolate the substrate 1S and the p-type wellsHPW1 and HPW2 from each other. When the substrate 1S is a p-type siliconsingle crystal substrate, a reverse bias is applied to a pn junction atan interface IF31 which is the interface between the portion of thesubstrate 1S underlying the portion thereof formed with the n-typeembedded well DNW and the n-type embedded well DNW and shown by thethick line in FIG. 6. In this manner, the substrate 1S and the n-typeembedded well DNW are electrically isolated from each other. Theelectrical isolation provided between the substrate 1S and the n-typeembedded well DNW provides electrical isolation between the substrate 1Sand the p-type wells HPW1 and HPW2.

Also, a voltage of, e.g., 0 V is applied to each of the p⁺-typesemiconductor region 4 a and the p-type well HPW2 through the conductorportion 7 a. At this time, since each of the p⁺-type semiconductorregion 4 a and the p-type well HPW2 is formed of a p-type semiconductor,as schematically shown by an arrow AW31, the potential differencebetween the p⁺-type semiconductor region 4 a and the p-type well HPW2 isequal to about 0 V. The arrow AW31 means that the potential differencebetween the starting end and terminating end of the arrow is equal toabout 0 V.

Also, a voltage of, e.g., about 0 V is applied from the control gateline CG1 to the n-type semiconductor region 13 c as one of the pair ofn-type semiconductor regions 13 of the MISFET QR for reading datathrough the conductor portion 7 d. At this time, as schematically shownby an arrow AW32, the potential difference between the n-typesemiconductor region 13C coupled to the conductor portion 7 d and thep-type well HPW2 is equal to about 0 V. The arrow AW32 means that thepotential difference between the starting end and terminating end of thearrow is equal to about 0 V.

Also, a positive voltage of, e.g., about 1 V is applied from the bitline RBL for reading data to the semiconductor region 13 e as the otherof the pair of n-type semiconductor regions 13 of the selection MISFETQS through the conductor portion 7 f.

Also, a voltage of, e.g., about 3 V as the power supply voltage Vcc isapplied from the selection line GS to the gate electrode FGS of theselection MISFET QS through the conductor portion 7 e.

On the other hand, a voltage of, e.g., 0 V is applied from each of thebit lines WBL for writing/erasing data to each of the p-typesemiconductor region 11 of the capacitor element CWE for writing/erasingdata, the n-type semiconductor region 12 thereof, and the p-type wellHPW1 thereof through each of the conductor portions 7 c. At this time,since each of the p-type semiconductor region 11 and the p-type wellHPW1 is formed of a p-type semiconductor, as schematically shown by anarrow AW33, the potential difference between the p-type semiconductorregion 11 and the p-type well HPW1 is equal to about 0 V. The arrow AW33means that the potential difference between the starting end andterminating end of the arrow is equal to about 0 V. Since the potentialdifference between the p-type semiconductor region 11 and the p-typewell HPW1 is equal to about 0 V, as schematically shown by an arrowAW34, the potential difference between the n-type semiconductor region12 and the p-type well HPW1 is also equal to about 0 V. The arrow AW34means that the potential difference between the starting end andterminating end of the arrow is equal to about 0 V.

Note that each of the voltages applied to the p-type semiconductorregion 11 of the capacitor element CWE for writing/erasing data, then-type semiconductor region 12 thereof, and the p-type well HPW1 thereofmay also be, e.g., the power supply voltage Vcc instead of 0 V.Alternatively, each of the foregoing voltages can also be applied inaccordance with a sweep method which continuously changes the appliedvoltage from a given voltage value to another voltage value.

On the other hand, a reverse bias is applied to a pn junction at aninterface IF32 which is the interface between the p-type well HPW1 andeach of the n-type well HNW and the n-type embedded well DNW and shownby the thick line in FIG. 6 to produce a potential differencecorresponding to, e.g., the power supply voltage Vcc. Additionally, areverse bias is applied to a pn junction at an interface IF33 which isthe interface between the p-type well HPW2 and each of the n-type wellHNW and the n-type embedded well DNW and shown by the thick line in FIG.6 to produce a potential difference corresponding to, e.g., the powersupply voltage Vcc.

Thus, to the n-type embedded well DNW, e.g., the power supply voltageVcc is applied. Also, in the state where a voltage of, e.g., 0 V isapplied to the p-type well HPW2 forming the lower electrode of thecapacitor element C serving also as the MISFET QR for reading data and avoltage of, e.g., 0 V is applied to the p-type well HPW1 forming thelower electrode of the capacitor element CWE for writing/erasing data,the selection MISFET QS is brought into an ON state. In such a state,the data stored in the selected memory cell, which is either 0 or 1depending on whether or not a drain current flows in the channel of theMISFET QR for reading data, is read. That is, on the basis of the valueof the current flowing between the semiconductor region 13 c as one ofthe pair of n-type semiconductor regions of the MISFET QR for readingdata and the n-type semiconductor region 13 d as the other of the pairof n-type semiconductor regions 13 thereof, the data stored in thememory cell MC1 is read.

Note that, in reading data, a ratio RC2 shown in the followingexpression (7), i.e., the ratio of the potential difference Vr to thetotal sum of the potential differences Vr and Vwe is defined as thecoupling ratio between the capacitor elements C and CWE.

RC2=Vr/(Vr+Vwe)  (7)

According to Embodiment 1 as described above, the capacitor element CWEfor writing/erasing data and the MISFET QR for reading data arerespectively formed in the p-type wells HPW1 and HPW2, which areseparate from each other, and isolated from each other by the n-typewell HNW and the n-type embedded well DNW. Also, rewriting of data isperformed in the capacitor element CWE for writing/erasing data. Thiseliminates the need to provide the memory cell MC1 of the flash memorywith the capacitor element C100 (see FIG. 14 described later) describedin Comparative Example 1 described later and allows a reduction in thesize of the semiconductor device.

Since the capacitor element CWE for writing/erasing data and the MISFETQR for reading data are formed respectively in the p-type wells HPW1 andHPW2, which are separate from each other, rewriting of data can bestabilized. This can improve the reliability of the operation of theflash memory.

In addition, since the rewriting of data can be performed with an FNtunnel current from the entire surface of the channel which consumesminimum power and is appropriate for single power supply rewriting at alow voltage, it is easy to provide a single power supply configurationusing an internal boosting circuit. This can increase the number oftimes data can be rewritten.

<Manufacturing Method of Semiconductor Device>

Next, a description will be given of a manufacturing method of thesemiconductor device in Embodiment 1. FIGS. 7 to 12 are main-portioncross-sectional views of the semiconductor device in Embodiment 1 duringa manufacturing process thereof. FIGS. 7 to 12 are cross-sectional viewsalong the line A-A of FIG. 2.

First, as shown in FIG. 7, the substrate 1S as a semiconductor substratemade of a silicon (Si) single crystal having a p-type conductivity typeis provided. On the main surface side of the substrate 1S, the n-typeembedded well DNW is formed by a photolithographic (hereinafter referredto simply as lithographic) process, an ion implantation process, and thelike. The lithographic process is a sequence of steps of forming anintended resist pattern through the application of a photoresist(hereinafter referred to simply as resist) film, the exposure thereof tolight, the development thereof, and the like. In the ion implantationprocess, using a resist pattern formed over the main surface of thesubstrate 1S through the lithographic process as a mask, an intendedimpurity is selectively introduced into the intended portion of thesubstrate 1S. The resist pattern is formed herein as such a pattern asto expose the region in which the impurity has been introduced and coverthe other region.

Subsequently, isolation trenches are formed in the isolation regions ofthe main surface of the substrate 1S. Then, in the isolation trenches,an insulating film is embedded to form the trench-shaped isolationportions TI. In this manner, active regions are defined in an area ARwewhere the capacitor element CWE for writing/erasing data is to beformed, an area ARr in which the MISFET QR for reading data is to beformed, and an area ARs in which the selection MISFET QS is to beformed. It may also be possible to form the isolation portions TI firstand then form the n-type embedded well DNW.

Next, as shown in FIG. 8, the p-type wells HPW1 and HPW2 and the n-typewell HNW are formed by a lithographic process, an ion implantationprocess, and the like. From the main surface side of the substrate 1S,into the n-type embedded well DNW, a p-type impurity such as, e.g.,boron (B) is ion-implanted by an ion implantation method to form thep-type wells HPW1 and HPW2. Also, from the main surface side of thesubstrate 1S, into the n-type embedded well DNW, an n-type impurity suchas, e.g., phosphorus (P) or arsenic (As) is implanted by an ionimplantation method to form the n-type well HNW.

Subsequently, the capacitor insulating film 10 a and the gate insulatingfilms 10 b and 10 c are formed by a thermal oxidation method or thelike. The capacitor insulating film 10 a is formed in the area ARwewhere the capacitor element CWE for writing/erasing data is to beformed. The gate insulating film 10 b is formed in the area ARr wherethe MISFET QR for reading data is to be formed. The gate insulating film10 c is formed in the area ARs where the selection MISFET QS is to beformed. The capacitor insulating film 10 a and the gate insulating films10 b and 10 c can also be formed by a CVD method or the like instead ofthe thermal oxidation method described above. As described above, it ispreferable that each of the capacitor insulating film 10 a and the gateinsulating films 10 b and 10 c preferably has a thickness of not lessthan 10 nm and not more than 20 nm which is, e.g., 12 nm.

Thereafter, over the main surface of the substrate 1S, a conductor film20 made of, e.g., low-resistance polysilicon is formed by a CVD methodor the like.

Then, as shown in FIG. 9, the conductor film 20 is patterned by, e.g., alithographic process and an etching process to form the capacitorelectrode FGC1 as the floating gate electrode FG, the gate electrode FGRas the floating gate electrode FG, and the gate electrode FGS. Thecapacitor electrode FGC1 is formed in the area ARwe where the capacitorelement CWE for writing/erasing data is to be formed. The gate electrodeFGR is formed in the area ARr where the MISFET QR for reading data is tobe formed. The gate electrode FGS is formed in the area ARs where theselection MISFET QS is to be formed.

Subsequently, in the area ARwe where the capacitor element CWE forwriting/erasing data is to be formed, in the portion of the p-type wellHPW1 which is located on one side of the capacitor electrode FGC1, thep⁻-type semiconductor region 11 a is formed by a lithographic process,an ion implantation method, and the like. Subsequently, in the area ARwewhere the capacitor element CWE for writing/erasing data is to beformed, in the portion of the p-type well HPW1 which is located on theother side of the capacitor electrode FGC1, the n⁻-type semiconductorregion 12 a is formed by a lithographic process, an ion implantationmethod, and the like. On the other hand, in the area ARr where theMISFET QR for reading data is to be formed, the n⁻-type semiconductorregions 13 a are formed by a lithographic process, an ion implantationmethod, and the like. In the area ARs where the selection MISFET QS isto be formed, the n⁻-type semiconductor regions 13 a are formed by alithographic process, an ion implantation method, and the like.

Next, as shown in FIG. 10, over the main surface of the substrate 1S, aninsulating film made of, e.g., silicon dioxide is deposited by a CVDmethod or the like and then etched back by anisotropic dry etching toform the sidewalls SW over the side surfaces of the capacitor electrodeFGC1 and the gate electrodes FGR and FGS.

Subsequently, in the area ARwe where the writing/erasing capacitorelement CWE is to be formed, in the portion of the p-type well HPW1which is located on one side of the capacitor electrode FGC1 formed withthe sidewalls SW, the p⁺-type semiconductor region 11 b is formed by alithographic process, an ion implantation method, and the like. At thistime, into, e.g., a region IPP1 (see FIG. 2), a p-type impurity such as,e.g., boron (B) is implanted by an ion implantation method. As a result,in the area ARwe, the p⁺-type semiconductor region 11 b is formed in theportion of the p-type well HPW1 which is located on one side of thecapacitor electrode FGC1 having the sidewalls SW formed over the sidesurfaces thereof, resulting in the formation of the p-type semiconductorregion 11 including the p⁻-type semiconductor region 11 a and thep⁺-type semiconductor region 11 b. Also, in the extension region of thep-type well HPW2, the p⁺-type semiconductor region 4 a is formed by alithographic step, an ion implantation method, and the like. At thistime, a p-type impurity such as, e.g., boron (B) is implanted into,e.g., a region IPP2 (see FIG. 2) by an ion implantation method.

Subsequently, in the area ARwe where the writing/erasing capacitorelement CWE is to be formed, the n⁺-type semiconductor region 12 b isformed by a lithographic step, an ion implantation method, and the like.At this time, an n-type impurity such as, e.g., phosphorus (P) orarsenic (As) is implanted into, e.g., a region IPN1 (see FIG. 2) by anion implantation method. As a result, in the area ARwe, in the portionof the p-type well HPW1 which is located on the other side of thecapacitor electrode FGC1 having the sidewalls SW formed over the sidesurfaces thereof, the n⁺-type semiconductor region 12 b is formed,resulting in the formation of the n-type semiconductor region 12including the n⁺-type semiconductor region 12 a and the n⁺-typesemiconductor region 12 b. Also, in the area ARwe where the capacitorelement CWE for writing/erasing data is to be formed, the capacitorelement CWE for writing/erasing data is formed.

In the area ARr where the MISFET QR for reading data is to be formed andin the area ARs where the selection MISFET QS is to be formed, then⁺-type semiconductor regions 13 b are formed by a lithographic step, anion implantation method, and the like. At this time, an n-type impuritysuch as, e.g., phosphorus (P) or arsenic (As) is implanted into, e.g., aregion IPN2 (see FIG. 2) by an ion implantation method. As a result, inthe area ARr where the MISFET QR for reading data is to be formed and inthe area ARs where the selection MISFET QS is to be formed, the n⁺-typesemiconductor regions 13 b are formed, resulting in the formation of then-type semiconductor regions 13 including the n⁻-type semiconductorregions 13 a and the n⁺-type semiconductor regions 13 b. Consequently,in the area ARr where the MISFET QR for reading data is to be formed,the MISFET QR for reading data is formed while, in the area ARs wherethe selection MISFET QS is to be formed, the selection MISFET QS isformed. The pair of n-type semiconductor regions 13 of the MISFET QR forreading data are the n-type semiconductor regions 13 c and 13 d. Thepair of n-type semiconductor regions 13 of the selection MISFET QS arethe n-type semiconductor regions 13 d and 13 e. At this time, in partsof the layer located over the n-type well HNW, the n⁺-type semiconductorregions 8 a are formed.

Next, as shown in FIG. 11, the silicide layers 5 a are selectivelyformed. Prior to the step of forming the silicide layers 5 a, over theupper surface of the floating gate electrode FG including the capacitorelectrode FGC1 and the gate electrode FGR, the cap insulating film 14 isformed while, over a part of the substrate 1S, an insulating film isformed to prevent the silicide layer 5 a from being formed in theportion.

Next, as shown in FIG. 12, over the main surface of the substrate 1S,the insulating film 6 a made of, e.g., silicon nitride is deposited by aCVD method or the like. Then, over the insulating film 6 a, theinsulating film 6 b made of, e.g., silicon dioxide is deposited to bethicker than the insulating film 6 a by a CVD method or the like. Theinsulating film 6 b is further subjected to a chemical mechanicalpolishing (CMP) process to have the upper surface thereof planarized. Inthis manner, the insulating film 6 including the insulating films 6 aand 6 b is formed.

Next, as shown in FIG. 3, in the insulating film 6, the contact holes CTare formed by a lithographic process and an etching process. Then, overthe main surface of the substrate 1S, a conductor film made of, e.g.,tungsten (W) or the like is deposited by a CVD method or the like andsubsequently polished by a CMP method or the like to form the conductorportions 7 a to 7 f in the contact holes CT. Thereafter, a typicalinterconnect forming process, an inspection process, and an assemblyprocess are performed to manufacture the semiconductor device.

<About Area Occupied by Memory Cell>

Next, a description will be given of the area occupied by a memory cellin Comparative Example 1 in which a MISFET for reading data and acapacitor element are separately provided.

FIG. 13 is a main-portion circuit diagram of a flash memory in asemiconductor device in Comparative Example 1. FIG. 14 is a plan view ofthe memory cell in the semiconductor device in Comparative Example 1.FIG. 15 is a cross-sectional view of the memory cell in thesemiconductor device in Comparative Example 1. FIGS. 14 and 15 show thememory cell corresponding to one bit. FIG. 15 is a cross-sectional viewalong the line A-A in FIG. 14. It is assumed that, in the plane shown inFIG. 14, the two directions crossing to each other, or preferablyorthogonal to each other, are an X-axis direction and a Y-axisdirection. In FIG. 14, for improved clarity of illustration, the drawingis partly hatched.

A flash memory in the semiconductor device in Comparative Example 1 hasa memory cell array MR100. In the memory cell array MR100 of the flashmemory in the semiconductor device in Comparative Example 1, in the samemanner as in the memory cell array MR1 in Embodiment 1, the plurality ofbit lines WBL for writing/erasing data each extending in the Y-axisdirection are arranged along the X-axis direction crossing, orpreferably orthogonal to, the Y-axis direction. Also, in the memory cellarray MR100, in the same manner as in the memory cell array MR1 inEmbodiment 1, the plurality of bit lines RBL for reading data eachextending in the Y-axis direction are arranged along the X-axisdirection. Also, in the memory cell array MR100, in the same manner asin the memory cell array MR1 in Embodiment 1, the plurality of selectionlines GS each extending along the X-axis direction and crossing the bitlines WLB and RBL are arranged along the Y-axis direction.

On the other hand, in the memory cell array MR100, unlike in the memorycell array MR1, a plurality of control gate lines CG100 each extendingalong the X-axis direction and crossing the bit lines WBL and RBL arearranged along the Y-axis direction. Also, in the memory cell arrayMR100, unlike in the memory cell array MR1, the plurality of sourcelines SL each extending along the X-direction and crossing the bit linesWBL and RBL are arranged along the Y-axis direction.

In the vicinity of the points of intersection between the bit lines WBLand RBL and the control gate lines CG100, the source lines SL, and theselection lines GS, memory cells MC100 each corresponding to one bit areelectrically coupled thereto.

Each of the memory cells MC100 includes the capacitor element CWE forwriting/erasing data, the MISFET QR for reading data, and the selectionMISFET QS, similarly to the memory cell MC1 in Embodiment 1. One of theelectrodes of the capacitor element CWE for writing/erasing data iselectrically coupled to one of the bit lines WBL for writing/erasingdata, in the same manner as in the memory cell MC1. The other electrodeof the capacitor element CWE for writing/erasing data is formed of apart of the floating gate electrode FG and electrically coupled to thegate electrode of the MISFET QR for reading data, in the same manner asin the memory cell MC1. On the other hand, the drain of the MISFET QRfor reading data is electrically coupled to one of the bit lines RBL forreading data via the selection MISFET QS. The source of the MISFET QRfor reading data is electrically coupled to one of the source lines SL.The gate electrode of the selection MISFET QS is electrically coupled toone of the selection lines GS.

On the other hand, unlike the memory cell MC1 in Embodiment 1, thememory cell MC100 includes the capacitor element C100. In the memorycell MC100, the other electrode of the capacitor element CWE forwriting/erasing data is formed of a part of the floating gate electrodeFG and electrically coupled to one of the electrodes of the capacitorelement C100, unlike in the memory cell MC1. The other electrode of thecapacitor element C100 is electrically coupled to the control gate lineCG100.

Thus, similarly to the memory cell MC1 of the flash memory in thesemiconductor device in Embodiment 1, the memory cell MC100 of the flashmemory in the semiconductor device in Comparative Example 1 has thefloating gate electrode FG, the capacitor element CWE forwriting/erasing data, and the MISFET QR for reading data. However,unlike the memory cell MC1 of the flash memory in the semiconductordevice in Embodiment 1, the memory cell MC100 of the flash memory in thesemiconductor device in Comparative Example 1 includes the capacitorelement C100. A description will be given below of the capacitor elementC100 and portions associated with the capacitor element C100.

In Comparative Example 1, the substrate 1S, the n-type embedded wellDNW, and the isolation portions TI each forming the semiconductor deviceare the same as in Embodiment 1. However, in Comparative Example 1, theisolation portions TI define the active regions L1, L2, L3, L4, andL105.

The n-type embedded well DNW is formed with the p-type wells HPW1, HPW2,and HPW103 and the n-type well HNW. The p-type wells HPW1 and HPW2 andthe n-type well HNW are the same as in Embodiment 1. However, inComparative Example 1, unlike in Embodiment 1, the p-type well HPW103 isformed. The p-type well HPW103 is located so as to be included in then-type embedded well DNW, while being electrically isolated from thep-type wells HPW1 and HPW2 by the n-type embedded well DNW and then-type well HNW. Also, the p-type well HPW103 is located so as to extendalong the p-type well HPW2. The p-type well HPW103 contains a p-typeimpurity such as, e.g., boron (B).

In Comparative Example 1, as shown in FIG. 14, the floating gateelectrode FG is formed in a state extending along the Y-axis directionso as to two-dimensionally overlap the p-type wells HPW1, HPW2, andHPW103. In the same manner as in Embodiment 1, at the position where thefloating gate electrode FG two-dimensionally overlaps the active regionL1 in the p-type well HPW1, the capacitor element CWE forwriting/erasing data is placed. Also, in the same manner as inEmbodiment 1, at the position where the floating gate electrode FGtwo-dimensionally overlaps the active region L2 in the p-type well HPW2,the MISFET QR for reading data is located.

On the other hand, at the position where the floating gate electrode FGtwo-dimensionally overlaps the active region L105 of the p-type wellHPW103, the capacitor element C100 is placed. The capacitor element C100includes the capacitor electrode FGC100, a capacitor insulating film 110d, a p-type semiconductor region 131, an n-type semiconductor region132, and the p-type well HPW103.

The capacitor electrode FGC100 is a portion formed of a part of thefloating gate electrode FG and forming the upper electrode of thecapacitor element C100.

The capacitor insulating film 100 d is made of, e.g., silicon dioxideand formed between the capacitor electrode FG100 and the substrate 1S,i.e., the p-type well HPW103.

The p-type semiconductor region 131 and the n-type semiconductor region132 are formed at respective positions in the p-type well HPW103 betweenwhich the capacitor electrode FGC100 is two-dimensionally interposed byself-alignment with the capacitor electrode FGC100.

The p-type semiconductor region 131 includes a channel-side p⁻-typesemiconductor region 131 a, and a p⁺-type semiconductor region 131 bcoupled to the p⁻-type semiconductor region 131 a. Each of the p⁻-typesemiconductor region 131 a and the p⁺-type semiconductor region 131 bcontains a p-type impurity such as, e.g., boron (B). The impurityconcentration of the p⁺-type semiconductor region 131 b is set higherthan the impurity concentration of the p⁻-type semiconductor region 131a. The p-type semiconductor region 131 is electrically coupled to aconductor portion 107 g in one of the contact holes CT formed in theinsulating film 6. The conductor portion 107 g is electrically coupledto the control gate line CG110. In a part of the top surface layer ofthe p⁺-type semiconductor region 131 b which is in contact with theconductor portion 107 g, the silicide layer 5 a may also be formed.

The n-type semiconductor region 132 includes a channel-side n-typesemiconductor region 132 a, and an n⁺-type semiconductor region 132 bcoupled to the n⁻-type semiconductor region 132 a. Each of the n⁻-typesemiconductor region 132 a and the n⁺-type semiconductor region 132 bcontains an n-type impurity such as, e.g., phosphorus (P) or arsenic(As). The impurity concentration of the n⁺-type semiconductor region 132b is set higher than the impurity concentration of the n⁻-typesemiconductor region 132 a. The n-type semiconductor region 132 iselectrically coupled to the conductor portion 107 g in one of thecontact holes CT formed in the insulating film 6. The conductor portion107 g is electrically coupled to the control gate line CG110. In a partof the top surface layer of the n⁺-type semiconductor region 132 b whichis in contact with the conductor portion 107 g, the silicide layer 5 amay also be formed.

Thus, in the semiconductor device in Comparative Example 1, the MISFETQR for reading data and the capacitor element C100 are separatelyprovided.

In Comparative Example 1, in writing data, a positive voltage of, e.g.,about 8 V is applied to the p-type well HPW103 of the capacitor elementC100, a voltage of, e.g., 0 V is applied to the p-type well HPW2 of theMISFET QR for reading data, and a negative voltage of, e.g., about −8 Vis applied to the p-type well HPW1 of the capacitor element CWE forwriting/erasing data. With such voltages being applied, electrons areinjected as an FN tunnel current from the p-type well HPW1 into thecapacitor electrode FGC1 through the capacitor insulating film 10 a.Through such an injection of electrons, data is written.

Also, in Comparative Example 1, in erasing data, a negative voltage of,e.g., about −8 V is applied to the p-type well HPW103 of the capacitorelement C100, a voltage of, e.g., 0 V is applied to the p-type well HPW2of the MISFET QR for reading data, and a positive voltage of, e.g.,about 8 V is applied to the p-type well HPW1 of the capacitor elementCWE for writing/erasing data. With such voltages being applied, theelectrons stored in the floating gate electrode FG as the capacitorelectrode FGC1 are released as an FN tunnel current into the p-type wellHPW1 through the capacitor insulating film 10 a. Through such a releaseof electrons, data is erased.

Further, in Comparative Example 1, in reading data, a voltage of, e.g.,about 0 V is applied to the p-type well HPW103, a voltage of, e.g., 0 Vis applied to the p-type well HPW2, and a voltage of, e.g., 0 V isapplied to the p-type well HPW1. With such voltages being applied, theselection MISFET QS is brought into the ON state. In such a state, thedata stored in the memory cell MC100 is read on the basis of the valueof a current flowing between the pair of n-type semiconductor regions 13of the MISFET QR for reading data.

It is assumed that a capacitance value CAPc100 is the capacitance valueof the capacitor element C100, a capacitance value CAPr is thecapacitance value of the capacitor element C serving also as the MISFETQR for reading data, and a capacitance value CAPwe is the capacitancevalue of the capacitor element CWE. It is also assumed that a potentialdifference Vc100 is the potential difference between the p-type wellHPW103 forming the lower electrode of the capacitor element C100 and thecapacitor electrode FGC100 forming the upper electrode of the capacitorelement C100. It is also assumed that a potential difference Vr is thepotential difference between the p-type well HPW2 forming the lowerelectrode of the capacitor element C serving also as the MISFET QR forreading data and the gate electrode FGR as the upper electrode of thecapacitor element C. It is also assumed that a potential difference Vweis the potential difference between the p-type well HPW1 forming thelower electrode of the capacitor element CWE and the capacitor electrodeFGC1 forming the upper electrode of the capacitor element CWE.

At this time, when the ratio of the potential difference Vwe to thetotal sum of the potential differences Vc100, Vr, and Vwe is defined asa coupling ratio RC101 between the capacitor elements C100, C, and CWE,it is possible to easily increase the coupling ratio RC101 inComparative Example 1. Accordingly, in the semiconductor device inComparative Example 1, it is possible to easily write data or easilyerase data.

On the other hand, in the semiconductor device in Comparative Example 1,in an area ARmc100 (see FIG. 14) where one of the memory cells MC100 isformed, the three p-type wells which are the p-type wells HPW1, HPW2,and HPW103 need to be placed. Accordingly, the area occupied by the areaARmc100 where one of the memory cells MC100 is formed is larger by thearea occupied by the p-type well HPW103.

In each of the memory cells MC100 in the semiconductor device inComparative Example 1, the p-type wells HPW1, HPW2, and HPW103 arearranged to be spaced apart from each other in the Y-axis direction. Ofthe n-type well HNW, the portion located between the p-type wells HPW1and HPW2 of one of the memory cells MC100 is assumed to be an n-typewell HNW1 and the portion located between the p-type well HPW2 of thememory cell MC100 and the p-type well HPW1 of another memory cell MC100adjacent to the memory cell MC100 in the Y-axis direction is assumed tobe an n-type well HNW2. On the other hand, the portion of the n-typewell HNW which is located between the p-type wells HPW2 and HPW103 isassumed to be an n-type well HNW103.

That is, in each of the memory cells MC100 in the semiconductor devicein Comparative Example 1, in the area ARmc100 (see FIG. 14) where thememory cell MC100 is formed, the three n-type wells which are the n-typewells HNW1, HNW2, and HNW3 need to be placed. The three n-type wellsHNW1, HNW2, and HNW103 do not directly contribute to the function ofwriting data in the flash memory, but need to be placed. Accordingly,the area occupied by the area ARmc100 where the memory cell MC100 isformed is larger by the area occupied by the three n-type wells HNW1,HNW2, and HNW103.

Thus, in the semiconductor device in Comparative Example 1, the areaoccupied by each of the memory cells is large. As a result, the capacityof the flash memory cannot easily be increased.

<Main Characteristic Features and Effects of Embodiment 1>

By contrast, the memory cell M1 in the semiconductor device inEmbodiment 1 includes the capacitor element CWE for writing/erasingdata, the MISFET QR for reading data, and the selection MISFET QS, butdoes not include the capacitor element C100, unlike the memory cellMC100 in the semiconductor device in Comparative Example 1. That is, theMISFET QR for reading data in the semiconductor device in Embodiment 1functions as each of the MISFET QR for reading data and the capacitorelement C100 in the semiconductor device in Comparative Example 1.

As a result, it is sufficient for only the two p-type wells which arethe p-type wells HPW1 and HPW2 to be placed in the area ARmc1 (see FIG.2) where one of the memory cells MC1 is placed. Unlike in ComparativeExample 1, the three p-type wells which are the p-type wells HPW1, HPW2,and HPW103 need not be placed. Accordingly, the area occupied by one ofthe memory cells MC1 in Embodiment 1 is smaller than the area occupiedby one of the memory cells MC100 in Comparative Example 1 by the areaoccupied by the p-type well HPW103 in Comparative Example 1.

Also, in each of the memory cells MC1 in the semiconductor device inEmbodiment 1, the p-type wells HPW1 and HPW2 are arranged to be spacedapart from each other in the Y-axis direction. Of the n-type well HNW,the portion located between the p-type wells HPW1 and HPW2 of one of thememory cells MC1 is assumed to be the n-type well HNW1 and the portionlocated between the p-type well HPW2 of the memory cell MC1 and thep-type well HPW1 of another memory cell MC1 adjacent to the memory cellMC1 in the Y-axis direction is assumed to be the n-type well HNW2.

That is, in each of the memory cells MC1 in the semiconductor device inEmbodiment 1, it is sufficient for only the two n-type wells which arethe n-type wells HNW1 and HNW2 to be placed in the area ARmc1 (see FIG.2) where the memory cell MC1 is formed. Accordingly, the area occupiedby the area ARmc1 where one of the memory cells MC1 is formed inEmbodiment 1 is smaller than the area occupied by the area ARmc100 whereone of the memory cells MC100 is formed in Comparative Example 1 by thearea occupied by the n-type well HNW103 in Comparative Example 1.

Thus, in the semiconductor device in Embodiment 1, it is possible toreduce the area occupied by one of the memory cells and easily increasethe capacity of the flash memory.

Note that, in Embodiment 1, it may also be possible to collectivelychange the conductivity types of the individual semiconductor regionssuch as, e.g., the semiconductor substrate 1S, the n-type embedded wellDNW, the p-type wells HPW1 and HPW2, the n-type well HNW, the p⁺-typesemiconductor region 4 a, the n⁺-type semiconductor region 8 a, thep-type semiconductor region 11, and the n-type semiconductor regions 12and 13 to the opposite polarities. Alternatively, it may also bepossible to change the polarities of the individual voltages applied ina data write operation (the same also applies to Embodiment 2).

Embodiment 2

Each of the memory cells in the semiconductor device in Embodiment 1includes the capacitor element for writing/erasing data, and the MISFETfor reading data. By contrast, each of memory cells in a semiconductordevice in Embodiment 2 includes an assist capacitor element in additionto the capacitor element for writing/erasing data and the MISFET forreading data.

<Circuit Configuration of Semiconductor Device>

FIG. 16 is a main-portion circuit diagram of a flash memory in thesemiconductor device in Embodiment 2. It is assumed that the twodirections crossing, or preferably orthogonal to, each other in theplane shown in FIG. 16 are an X-axis direction and a Y-axis direction.

The flash memory in the semiconductor device in Embodiment 2 has amemory cell array MR2. In the memory cell array MR2, in the same manneras in the memory cell array MR1 in Embodiment 1, the plurality of bitlines WBL for writing/erasing data each extending in the Y-axisdirection are arranged along the X-axis direction crossing, orpreferably orthogonal to, the Y-axis direction. Also, in the memory cellarray MR2, in the same manner as in the memory cell array MR1, theplurality of bit lines RBL for reading data each extending in the Y-axisdirection are arranged along the X-axis direction. Also, in the memorycell array MR2, in the same manner as in the memory cell array MR1, theplurality of control gate lines CG1 (source lines SL) and the pluralityof control gate lines CG0 (p-type well HPW2) each extending along theX-axis direction and crossing the bit lines WBL and RBL are arrangedalong the Y-axis direction. Also, in the memory cell array MR2, in thesame manner as in the memory cell array MR1, the plurality of selectionlines GS each extending along the X-axis direction and crossing the bitlines WBL and RBL are arranged along the Y-axis direction.

On the other hand, in the memory cell array MR2 in Embodiment 2, unlikein the memory cell array MR1, a plurality of control gate lines CG2 eachextending along the X-axis direction and crossing the bit lines WBL andRBL are arranged along the Y-axis direction.

In the vicinity of the points of intersection between the bit lines WBLand RBL and the control gate lines CG1 and CG2 and the selection linesGS, memory cells MC2 each corresponding to one bit are electricallycoupled thereto. FIG. 16 illustrates the case where one bit is formed ofone of the memory cells MC2.

Similarly to each of the memory cells MC1 in Embodiment 1, each of thememory cells MC2 includes the capacitor element CWE for writing/erasingdata, the MISFET QR for reading data, and the selection MISFET QS.

In the same manner as in each of the memory cells MC1, one of theelectrodes of the capacitor element CWE for writing/erasing data iselectrically coupled to one of the bit lines WBL for writing/erasingdata. The other electrode of the capacitor element CWE forwriting/erasing data is formed of a part of the floating gate electrodeFG, which will be described using FIGS. 17 and 18 described later. Thegate electrode of the MISFET QR for reading data is formed of anotherpart of the floating gate electrode FG. Consequently, in the same manneras in the memory cell MC1, the other electrode of the capacitor elementCWE for writing/erasing data is electrically coupled to the gateelectrode of the MISFET QR for reading data. On the other hand, thedrain of the MISFET QR for reading data is electrically coupled to oneof the bit lines RBL for reading data via the selection MISFET QS. Thesource of the MISFET QR for reading data is electrically coupled to thecontrol gate line CG1, which is used also as the source line SL. Thegate electrode of the selection MISFET QS is electrically coupled to oneof the selection lines GS.

However, unlike the memory cell MC1 in Embodiment 1, the memory cell MC2includes an assist capacitor element CA. One of the electrodes of theassist capacitor element CA is electrically coupled to the control gateline CG2. The other electrode of the assist capacitor element CA isformed of a part of the floating gate electrode FG. Consequently, theother electrode of the assist capacitor element CA is electricallycoupled to the other electrode of the capacitor element CWE forwriting/erasing data and to the gate electrode of the MISFET QR forreading data.

<Configuration of Memory Cell>

Next, a description will be given of a configuration of each of thememory cells of the flash memory in the semiconductor device inEmbodiment 2. FIG. 17 is a plan view of each of the memory cells in thesemiconductor device in Embodiment 2. FIG. 18 is a cross-sectional viewof the memory cell in the semiconductor device in Embodiment 2. Each ofFIGS. 17 and 18 shows the memory cell corresponding to one bit. FIG. 18is a cross-sectional view along the line A-A in FIG. 17.

It is assumed that, in the plane shown in FIG. 17, the two directionscrossing each other, or preferably orthogonal to each other, are theX-axis direction and the Y-axis direction. FIG. 17 shows the memory cellin a see-through state where the conductor portions 7 a to 7 g, theinsulating film 6, the cap insulating film 14, the silicide layer 5 a,the sidewalls SW, and the isolation portions TI have been removed. FIG.17 shows only the outer periphery of the cap insulating film 14. Forimproved clarity of illustration, FIG. 17 is partly hatched.

As described above, each of the memory cells MC2 of the flash memory inthe semiconductor device in Embodiment 2 includes the floating gateelectrode FG, the capacitor element CWE for writing/erasing data, andthe MISFET QR for reading data, similarly to each of the memory cellsMC1 of the flash memory in the semiconductor device in Embodiment 1.However, unlike the memory cell MC1 in Embodiment 1, the memory cell MC2in Embodiment 2 includes the assist capacitor element CA. Accordingly, adescription will be given below mainly of the assist capacitor elementCA and portions associated with the assist capacitor element CA.

The substrate 1S, the n-type embedded well DNW, and the isolationportions TI each forming the semiconductor device are the same as inEmbodiment 1. However, in Embodiment 2, the isolation portions TI definethe active regions L1, L2, L3, L4, and L5.

In the n-type embedded well DNW, the p-type wells HPW1 and HPW2 and then-type well HNW are formed. The p-type wells HPW1 and HPW2 and then-type well HNW are the same as in Embodiment 1.

In the same manner as in Embodiment 1, in Embodiment 2 also, thefloating gate electrode FG is formed in a state extending along theY-axis direction so as to two-dimensionally overlap the p-type wellsHPW1 and HPW2, as shown in FIG. 17. In the same manner as in Embodiment1, at the position where the floating gate electrode FGtwo-dimensionally overlaps the active region L1 of the p-type well HPW1,the capacitor element CWE for writing/erasing data is placed. Also, inthe same manner as in Embodiment 1, at the position where the floatinggate electrode FG two-dimensionally overlaps the active region L2 of thep-type well HPW2, the MISFET QR for reading data is placed.

On the other hand, at the position where the floating gate electrode FGtwo-dimensionally overlaps the active region L5 of the n-type well HNW1as the portion of the n-type well HNW which is located between thep-type wells HPW1 and HPW2, the assist capacitor element CA as thecapacitor element is placed. The assist capacitor element CA includes acapacitor electrode FGC2, a capacitor insulating film 10 d, p-typesemiconductor regions 21, and the n-type well HNW.

The capacitor electrode FGC2 is formed of a part of the floating gateelectrode FG. Here, of the n-type well HNW, the portion located betweenthe p-type wells HPW1 and HPW2 is assumed to be the n-type well HNW1. Atthis time, the capacitor electrode FGC2 is formed of the portion of thefloating gate electrode FG which is formed at the positiontwo-dimensionally overlapping the active region L5 of the n-type wellHNW1. The capacitor electrode FGC2 is the portion forming the upperelectrode of the assist capacitor element CA.

The capacitor insulating film 10 d is made of, e.g., silicon dioxide andformed between the capacitor electrode FGC2 and the substrate 1S, i.e.,the n-type well HNW1. The capacitor insulating film 10 d is formed by,e.g., a thermal oxidation process and has a thickness of, e.g., about 12nm.

The pair of p-type semiconductor regions 21 are formed at respectivepositions in the n-type well HNW1 between which the capacitor electrodeFGC2 is two-dimensionally interposed by self-alignment with thecapacitor electrode FGC2.

Each of the p-type semiconductor regions 21 includes a channel-sidep⁻-type semiconductor region 21 a, and a p⁺-type semiconductor region 21b coupled to the p⁻-type semiconductor region 21 a. The p⁻-typesemiconductor region 21 a and the p⁺-type semiconductor region 21 bcontain impurities each having the same conductivity type such as, e.g.,boron (B). However, the impurity concentration of the p⁺-typesemiconductor region 21 b is set higher than the impurity concentrationof the p⁻-type semiconductor region 21 a. The p-type semiconductorregions 21 are electrically coupled to the conductor portions 7 g in thecontact holes CT formed in the insulating film 6. The conductor portions7 g are electrically coupled to the control gate lines CG2. In parts ofthe top surface layers of the p⁺-type semiconductor regions 21 b whichare in contact with the conductor portions 7 g, the silicide layers 5 amay also be formed.

Each of the p-type semiconductor regions 21 is electrically coupled tothe n-type well HNW1. Accordingly, the n-type well HNW1 is the portionforming the lower electrode of the assist capacitor element CA.

In Embodiment 2 also, in the same manner as in Embodiment 1, the lengthLNwe of the capacitor electrode FGC1 of the capacitor element CWE forwriting/erasing data in the X-axis direction is smaller than the lengthLNr of the gate electrode FGR of the MISFET QR for reading data in theX-axis direction. This allows the capacitance value of the capacitorelement CWE for writing/erasing data to be set smaller than thecapacitance value of the capacitor element C serving also as the MISFETQR for reading data. Also, in the same manner as in Embodiment 1, bysetting the capacitance value of the capacitor element CWE smaller thanthe capacitance value of the capacitor element C, writing/erasing ofdata can easily be performed.

In Embodiment 2 also, such a portion is not provided in which the lengthof the capacitor electrode FGC100 of the capacitor element C100 (seeFIG. 14) described above in Comparative Example 1, i.e., the length ofthe floating gate electrode FG in the X-axis direction is larger thanthe length of the gate electrode FGR of the MISFET QR for reading datain the X-axis direction. In such a case, it is preferable that the gateelectrode FGR of the MISFET QR for reading data is a portion where thelength of the floating gate electrode FG in the X-axis direction islargest.

On the other hand, in Embodiment 2, unlike in Embodiment 1, the assistcapacitor element CA is formed. Accordingly, the capacitance value ofthe capacitor element CWE for writing/erasing data can easily be setsmaller than the sum of the capacitance value of the capacitor element Cserving also as the MISFET QR for reading data and the capacitance valueof the assist capacitor element CA. As will be described in an exampleof a data write operation in the flash memory described later, bysetting the capacitance value of the capacitor element CWE smaller thanthe sum of the capacitance value of the capacitor element C and thecapacitance value of the assist capacitor element CA, the coupling ratioin writing data can easily be increased. This allows data to be moreeasily written than in Embodiment 1.

Preferably, the length LNwe of the capacitor electrode FGC1 of thecapacitor element CWE for writing/erasing data in the X-axis directionis smaller than a length LNa of the capacitor electrode FGC2 of theassist capacitor element CA in the X-axis direction. Accordingly, thecapacitance value of the capacitor element CWE for writing/erasing datacan more easily be set smaller than the sum of the capacitance value ofthe capacitor element C serving also as the MISFET QR for reading dataand the capacitance value of the assist capacitor element CA. Thisallows data to be far more easily written than in Embodiment 1.

In Embodiment 2 also, in the same manner as in Embodiment 1, it ispreferable that the length LNs of the gate electrode FGS of theselection MISFET QS in the X-axis direction is larger than the lengthLNr of the gate electrode FGR in the X-axis direction. This can preventor inhibit a punch-through in the selection MISFET QS and reduce aleakage current in the OFF state, i.e., OFF leakage current. On theother hand, in the MISFET QR for reading data, it is less necessary toprevent or inhibit a punch-through than in the selection MISFET QS.Accordingly, the length LNr of the gate electrode FGR in the X-axisdirection may also be smaller than the length LNs of the gate electrodeFGS in the X-axis direction.

In Embodiment 2 also, in the same manner as in Embodiment 1, it ispreferable that the width WDwe of the portion of the capacitor electrodeFGC1 which is interposed between the p-type semiconductor region 11 andthe n-type semiconductor region 12 in the Y-axis direction is smallerthan the width WDr of the portion of the gate electrode FGR which isinterposed between the n-type semiconductor regions 13 c and 13 d in theY-axis direction. As a result, the width WDr of the gate electrode FGRin the Y-axis direction relatively increases to allow an increase in theread current flowing in the MISFET QR for reading data and allow forhigh-speed reading.

<Example of Data Write Operation>

Next, a description will be given of an example of a data writeoperation in such a flash memory. FIG. 19 is a cross-sectional viewshowing an example of voltages applied to the individual portions of thememory cell in a data write operation in the flash memory in Embodiment2. FIG. 19 is a cross-sectional view along the line A-A in FIG. 17.

In writing data, on the portions other than the assist capacitor elementCA, generally the same operation as described in Embodiment 1 using FIG.4 is performed. First, by the same operation as in Embodiment 1, thesubstrate 1S and the p-type wells HPW1 and HPW2 are electricallyisolated from each other. Also, by the same operation as in Embodiment1, a positive voltage of, e.g., about 8 V is applied to the p-type wellHPW2 of each of the MISFET QR for reading data and the selection MISFETQS, while a negative voltage of, e.g., about −8 V is applied to thep-type well HPW1 of the capacitor element CWE for writing/erasing data.In addition, to the gate electrode FGS of the selection MISFET QS, apositive voltage of, e.g., about 8 V is applied or the gate electrodeFGS is brought into the open state (shown as “Open” in FIG. 19).

On the other hand, in Embodiment 2, unlike in Embodiment 1, a positivevoltage of, e.g., about 8 V is applied from each of the control gatelines CG2 to each of the p-type semiconductor regions 21 of the assistcapacitor element CA through each of the conductor portions 7 g. At thistime, as schematically shown by each of arrows AW17, the potentialdifference between each of the p-type semiconductor regions 21 coupledto the conductor portions 7 g and the n-type well HNW1 is equal to about0 V. The arrow AW17 means that the potential difference between thestarting end and terminating end of the arrow is equal to about 0 V.

Thus, to each of the n-type embedded well DNW and the p-type well HPW2forming the lower electrode of the capacitor element C serving also asthe MISFET QR for reading data, a positive voltage of, e.g., about 8 Vis applied. On the other hand, to the p-type well HPW1 forming the lowerelectrode of the capacitor element CWE for writing/erasing data, anegative voltage of, e.g., about −8 V, i.e., voltage having the polarityopposite to the polarity of the voltage applied to the p-type well HPW2is applied via the p-type semiconductor region 11. Also, to the n-typewell HNW1 of the assist capacitor element CA, a positive voltage of,e.g., about 8 V is applied.

By the application of such voltages, the p-type wells HPW1 and HPW2 areindividually controlled and the n-type well HNW1 is controlled to havethe same potential as that of the p-type well HPW2. As a result,electrons e⁻ are injected as an FN tunnel current from the entiresurface of the channel from the p-type well HPW1 into the capacitorelectrode FGC1 through the capacitor insulating film 10 a or holes arereleased as an FN tunnel current from the capacitor electrode FGC. Inthis manner, data is written.

In writing data, the capacitor element C and the assist capacitorelement CA are coupled in parallel to each other via the floating gateelectrode FG, and the capacitor element CWE is coupled in series to eachof the capacitor element C and the assist capacitor element CA via thefloating gate electrode FG.

In Embodiment 2 also, in the same manner as in Embodiment 1, it isassumed that the capacitance value CAPr is the capacitance value of thecapacitor element C and the capacitance value CAPwe is the capacitancevalue of the capacitor element CWE. It is also assumed that thepotential difference Vr is the potential difference between the p-typewell HPW2 forming the lower electrode of the capacitor element C and thegate electrode FGR forming the upper electrode of the capacitor elementC. It is also assumed that the potential difference Vwe is the potentialdifference between the p-type well HPW1 forming the lower electrode ofthe capacitor element CWE and the capacitor electrode FGC1 forming theupper electrode of the capacitor element CWE.

On the other hand, in Embodiment 2, it is assumed that a capacitancevalue CAPa is the capacitance value of the assist capacitor element CAand a potential difference Va is the potential difference between then-type well HNW1 forming the lower electrode of the assist capacitorelement CA and the capacitor electrode FGC2 forming the upper electrodeof the assist capacitor element CA. As described above, the capacitorelement C and the assist capacitor element CA are coupled in parallel toeach other via the floating gate electrode FG. Accordingly, thepotential difference Va is equal to the potential difference Vr.

At this time, by increasing the ratio of the sum of the capacitancevalues CAPr and CAPa to the total sum of the capacitance values CAPr,CAPa, and CAPwe, it is possible to increase the coupling ratio RC1 shownin the foregoing expression (1) and increase the potential differenceVwe in the capacitor element CWE. As a result, in the capacitor elementCWE, electrons are more likely to be injected as an FN tunnel currentinto the capacitor electrode FGC1 or holes are more likely to bereleased as an FN tunnel current from the capacitor electrode FGC1.

Preferably, the capacitor element C, the assist capacitor element CA,and the capacitor element CWE are designed such that the capacitancevalues CAPr, CAPa, and CAPwe satisfy the following expression (8). Bysatisfying the following expression (8), it is possible to set thecoupling ratio RC1 larger than 0.5 and set the potential difference Vwelarger than each of the potential differences Vr and Va, as shown in theforegoing expression (1). As a result, in the capacitor element CWE,electrons are more likely to be injected as an FN tunnel current intothe capacitor electrode FGC1 or holes are more likely to be released asan FN tunnel current from the capacitor electrode FGC1 than in thecapacitor element C.

CAPr+CAPa>CAPwe  (8)

In the same manner as in Embodiment 1, it is assumed that the length LNris the length of the gate electrode FGR in the X-axis direction and thewidth WDr is the width of the gate electrode FGR in the Y-axisdirection. It is also assumed that the length LNwe is the length of thecapacitor electrode FGC1 in the X-axis direction and the width WDwe isthe width of the capacitor electrode FGC1 in the Y-axis direction. Atthis time, the area Sr occupied by the gate electrode FGR is given bythe foregoing expression (4), and the area Swe occupied by the capacitorelectrode FGC1 is given by the foregoing expression (5).

It is also assumed that the length LNa is the length of the capacitorelectrode FGC2 in the X-axis direction and a width WDa is the width ofthe capacitor electrode FGC2 in the Y-axis direction. At this time, anarea Sa occupied by the capacitor electrode FGC2 is given by thefollowing expression (9). When, e.g., each of the capacitor insulatingfilms 10 a and 10 d and the gate insulating film 10 b has an equalthickness and an equal dielectric constant, by satisfying the followingexpression (10), it is possible to satisfy the foregoing expression (8).

Sa=LNa×WDa  (9)

Sr+Sa>Swe  (10)

The graph of FIG. 20 shows the coupling ratio when the ratio between thecapacitance value CAPr of the MISFET QR for reading data and thecapacitance value CAPwe of the capacitor element CWE for writing/erasingdata is held constant and the ratio of the capacitance value CAPa of theassist capacitor element CA to the capacitance value CAPr of the MISFETQR for reading data is varied. The abscissa in FIG. 20 represents theratio of the capacitance value CAPa to the capacitance value CAPr. Theordinate in FIG. 20 shows the coupling ratio. FIG. 20 shows the casewhere the ratio between the capacitance values CAPr and CAPwe satisfiesCapacitance Value CAPr:Capacitance Value CAPwe=0.686:0.068.

In the graph of FIG. 20, the curve referred to as “Writing” shows thecoupling ratio RC1 in writing data. Also, the case where the ratio ofthe capacitance value CAPa to the capacitance value CAPr is 0corresponds to the case where the assist capacitor element CA is notformed, i.e., Embodiment 1.

In the graph of FIG. 20, as shown by the curve referred to as “Writing”,the coupling ratio RC1 in writing data in the case where the assistcapacitor element CA is formed (Embodiment 2) is higher than thecoupling ratio RC1 in writing data in the case where the assistcapacitor element CA is not formed (Embodiment 1). Therefore, by formingthe assist capacitor element CA, in the capacitor element CWE forwriting/erasing data, it is possible to easily inject electrons as an FNtunnel current from the p-type well HPW1 into the capacitor electrodeFGC1 through the capacitor insulating film 10 a and easily write data.

Also, as shown by the curve referred to as “Writing” in FIG. 20, as thecapacitance value CAPa of the assist capacitor element CA increases, thecoupling ratio RC increases. Therefore, by increasing the capacitancevalue CAPa of the assist capacitor element CA, it is possible to moreeasily inject electrons as an FN tunnel current from the p-type wellHPW1 into the capacitor electrode FGC1 through the capacitor insulatingfilm 10 a in the capacitor element CWE for writing/erasing data and moreeasily write data.

FIG. 21 is a cross-sectional view showing an example of voltages appliedto the individual portions of the memory cell in a data erase operationin the flash memory in Embodiment 2. FIG. 21 is a cross-sectional viewalong the line A-A in FIG. 17.

In erasing data, on the portions other than the assist capacitor elementCA, generally the same operation as described in Embodiment 1 using FIG.5 is performed. First, by the same operation as in Embodiment 1, thesubstrate 1S and the p-type wells HPW1 and HPW2 are electricallyisolated from each other. Also, by the same operation as in Embodiment1, a negative voltage of, e.g., about −8 V is applied to the p-type wellHPW2 of each of the MISFET QR for reading data and the selection MISFETQS, while a positive voltage of, e.g., about 8 V is applied to thep-type well HPW1 of the capacitor element CWE for writing/erasing data.In addition, to the gate electrode FGS of the selection MISFET QS, anegative voltage of, e.g., about −8 V is applied or the gate electrodeFGS is brought into the open state (shown as “Open” in FIG. 21).

On the other hand, in Embodiment 2, unlike in Embodiment 1, a voltageof, e.g., 0 V is applied from each of the control gate lines CG2 to eachof the p-type semiconductor regions 21 of the assist capacitor elementCA through each of the conductor portions 7 g. At this time, to a pnjunction at an interface IF23 which is the interface between each of thep-type semiconductor regions 21 and the n-type well HNW1 and shown bythe thick line in FIG. 21, a reverse bias is applied and a potentialdifference of, e.g., about 8 V is produced. Also, in the layer locatedover the portion where the capacitor electrode FGC2 two-dimensionallyoverlaps the active region L5 of the n-type well HNW1, i.e., in a regionCHa corresponding to a channel, a depletion layer DL is formed. Then, toa pn junction at the interface IF23 which is the interface between thedepletion layer DL and the n-type well HNW1 and shown by the thick linein FIG. 21, a reverse bias is applied and a potential difference of,e.g., about 8 V is produced.

Thus, to the n-type embedded well DNW, the voltage having the samepolarity as the polarity of the voltage applied to the n-type embeddedwell DNW in writing data is applied. To the p-type well HPW2 forming thelower electrode of the capacitor element C serving also as the MISFET QRfor reading data, a negative voltage of, e.g., about −8 V, i.e., voltagehaving the polarity opposite to the polarity of the voltage applied tothe n-type embedded well DNW in writing data is applied. To the p-typewell HPW1 forming the lower electrode of the capacitor element CWE forwriting/erasing data, a positive voltage of, e.g., about 8 V, i.e.,voltage having the same polarity as the polarity of the voltage appliedto the n-type embedded well DNW in writing data is applied. Also, to then-type well HNW1 of the assist capacitor element CA, a voltage of, e.g.,0 V is applied.

By the application of such voltages, the p-type wells HPW1 and HPW2 areindividually controlled and the n-type well HNW1 is controlled to havethe same potential as that of the p-type well HPW1. As a result, theelectrons e stored in the floating gate electrode FG as the capacitorelectrode FGC1 are released as an FN tunnel current from the entiresurface of the channel into the p-type well HPW1 through the capacitorinsulating film 10 a or holes are injected as an FN tunnel current intothe capacitor electrode FGC1. In this manner, data is erased.

When the depletion layer DL is not formed in the region CH1, thepotential difference between the p-type well HPW1 forming the lowerelectrode of the capacitor element CWE and the region CHa is equal toabout 0 V. At this time, the capacitor element CWE and the assistcapacitor element CA are coupled in parallel to each other via thefloating gate electrode FG so that the capacitor element C is coupled inseries to each of the capacitor element CWE and the assist capacitorelement CA via the floating gate electrode FG. Consequently, thecoupling ratio RC1 shown in the foregoing expression (1) decreases.

On the other hand, when a voltage of, e.g., 0 V is applied to each ofthe p-type semiconductor regions 21 and the depletion layer DL is formedin the region CHa, the positive voltage of, e.g., about 8 V applied tothe n-type well HNW is not applied to the region CHa. As a result, thecoupling ratio RC1 shown in the foregoing expression (1) becomes higherthan when the depletion layer DL is not formed in the region CHa.Accordingly, when the depletion layer DL is formed in the region CHa, inthe capacitor element CWE, electrons are more likely to be released asan FN tunnel current from the capacitor electrode FGC1 or holes are morelikely to be injected as an FN tunnel current into the capacitorelectrode FGC1 than when the depletion layer DL is not formed in theregion CHa.

It is assumed here that a voltage Vaa is the voltage applied to each ofthe p-type semiconductor regions 21 of the assist capacitor element CAand a voltage Vwea is the voltage applied to the p-type well HPW1forming the lower electrode of the capacitor element CWE. The graph ofFIG. 20 shows the coupling ratio RC1 when the ratio of the capacitancevalue CAPa to the capacitance value CAPr is varied in each of the caseswhere the voltage Vaa is 0 V (Vaa=0) and where the voltage Vaa is equalto the voltage Vwea (Vaa=Vwea).

In FIG. 20, the curve referred to as “Erasing (Vaa=0)” shows the casewhere the voltage Vaa is 0 V. Also, in FIG. 20, the curve referred to as“Erasing (Vaa=Vwea)” shows the case where the voltage Vaa is equal tothe voltage Vwea.

As shown by the curve referred to as “Erasing (Vaa=0)” in FIG. 20 andthe curve referred to as “Erasing (Vaa=Vwea)” in FIG. 20, in the casewhere the voltage Vaa is 0 V, the coupling ratio RC is higher than inthe case where the voltage Vaa is equal to Vwea. Accordingly, byapplying a voltage of, e.g., 0 V to each of the p-type semiconductorregions 21, it is possible to easily inject electrons as an FN tunnelcurrent from the p-type well HPW1 of the capacitor element CWE forwriting/erasing data into the floating gate electrode FG as thecapacitor electrode FGC1 through the capacitor insulating film 10 a andeasily erase data.

FIG. 22 is a cross-sectional view showing an example of voltages appliedto the individual portions of the memory cell in a data read operationin the flash memory in Embodiment 2. FIG. 22 is a cross-sectional viewalong the line A-A in FIG. 17.

In reading data, on the portions other than the assist capacitor elementCA and the capacitor element CWE, generally the same operation asdescribed in Embodiment 1 using FIG. 6 is performed. First, by the sameoperation as in Embodiment 1, the substrate 1S and the p-type wells HPW1and HPW2 are electrically isolated from each other. Also, by the sameoperation as in Embodiment 1, a voltage of 0 V is applied to the p-typewell HPW2 of the MISFET QR for reading data, while a voltage of, e.g.,about 3 V as a power supply voltage Vcc is applied to the gate electrodeFGS of the selection MISFET QS.

On the other hand, in Embodiment 2, unlike in Embodiment 1, a voltageof, e.g., about 3 V as the power supply voltage Vcc is applied from eachof the bit lines WBL for writing/erasing data to each of the p-typesemiconductor region 11 of the capacitor element CWE for writing/erasingdata, the n-type semiconductor region 12 thereof, and the p-type wellHPW1 thereof via each of the conductor portions 7 c. At this time, sinceeach of the p-type semiconductor region and the p-type well HPW1 isformed of a p-type semiconductor, as schematically shown by an arrowAW33, the potential difference between the p-type semiconductor region11 and the p-type well HPW1 is equal to about 0 V. The arrow AW33 meansthat the potential difference between the starting end and terminatingend of the arrow is equal to about 0 V. Since the potential differencebetween the p-type semiconductor region 11 and the p-type well HPW1 isequal to about 0 V, as schematically shown by an arrow AW34, thepotential difference between the n-type semiconductor region 12 and thep-type well HPW1 is also equal to about 0 V. The arrow AW34 means thatthe potential difference between the starting end and terminating end ofthe arrow is equal to about 0 V.

Also, in Embodiment 2, unlike in Embodiment 1, a voltage of, e.g., about3 V as the power supply voltage Vcc is applied from each of the controlgate lines CG2 to each of the p-type semiconductor regions 21 of theassist capacitor element CA through each of the conductor portions 7 g.At this time, as schematically shown by arrows AW35 and AW36, thepotential difference between each of the p-type semiconductor regions 21and the n-type well HNW1 is equal to about 0 V. Each of the arrows AW35and AW36 means that the potential difference between the starting endand terminating end of the arrow is equal to about 0 V.

Note that, since the forward bias is applied to a pn junction at theinterface between the p-type well HPW1 and the n-type well HNW1, asschematically shown by an arrow AW37, the potential difference betweenthe p-type well HPW1 and the n-type well HNW1 is equal to about 0 V. Thearrow AW37 means that the potential difference between the starting endand terminating end of the arrow is equal to about 0 V.

Thus, to the n-type embedded well DNW, e.g., the power supply voltageVcc is applied. Also, to the p-type well HPW2 forming the lowerelectrode of the capacitor element C serving also as the MISFET QR forreading data, a voltage of, e.g., 0 V is applied while, to the p-typewell HPW1 forming the lower electrode of the capacitor element CWE forwriting/erasing data, e.g., the power supply voltage Vcc is applied.Also, in the state where, e.g., the power supply voltage Vcc is appliedto the n-type well HNW1 of the assist capacitor element CA, theselection MISFET QS is brought into the ON state. In such a state, thedata stored in the selected memory cell, which is either 0 or 1depending on whether or not a drain current flows in the channel of theMISFET QR for reading data, is read. That is, on the basis of the valueof the current flowing between the semiconductor region 13 c as one ofthe pair of n-type semiconductor regions of the MISFET QR for readingdata and the n-type semiconductor region 13 d as the other of the pairof n-type semiconductor regions 13 thereof, the data stored in thememory cell MC2 is read.

By the application of such voltages, in reading data, the capacitorelement CWE and the assist capacitor element CA are coupled in parallelto each other via the floating gate electrode FB so that the capacitorelement C is coupled in series to each of the capacitor element CWE andthe assist capacitor element CA via the floating gate electrode FG.

At this time, by increasing the ratio of the sum of the capacitancevalues CAPwe and CAPa to the total sum of the capacitance values CAPr,CAPa, and CAPwe, it is possible to increase the coupling ratio RC2 shownin the foregoing expression (7) and increase the potential difference Vrin the capacitor element C. This can improve reliability in reading thedata stored in the memory cell MC2.

The curve referred to as “Reading (Selected)” in the graph of FIG. 20shows the coupling ratio RC2 in reading.

As shown by the curve referred to as “Reading (Selected)” in the graphof FIG. 20, the coupling ratio RC2 in reading data in the case where theassist capacitor element CA is formed (Embodiment 2) is higher than thecoupling ratio RC2 in reading data in the case where the assistcapacitor element CA is not formed (Embodiment 1). In addition, as thecapacitance value CAPa of the assist capacitor element CA increases, thecoupling ratio RC2 increases. For example, in the case where the assistcapacitor element CA is not formed, the coupling ratio RC2 is less than0.1. By contrast, in the case where the assist capacitor element Ca isformed and the ratio of the capacitance value CAPa of the assistcapacitor element CA to the capacitance value CAPr of the MISFET QR forreading data is not less than 0.5, the coupling ratio RC2 is higher than0.3. By thus forming the assist capacitor element CA, it is possible toincrease the potential difference between the p-type well HPW2 formingthe lower electrode of the capacitor element C serving also as theMISFET QR for reading data and the gate electrode FGR forming the upperelectrode thereof and improve reliability in reading the data stored inthe memory cell MC2.

Note that the curve referred to as “Reading (Non-Selected)” in the graphof FIG. 20 shows the coupling ratio RC2 in reading in the non-selectedmemory cell MC2, i.e., the memory cell MC2 in which the selection MISFETQS is not in the ON state. In this case, to the other n-typesemiconductor region 13 e of the selection MISFET QS, a voltage of,e.g., 0 V is applied from the bit line RBL for reading data through theconductor portion 7 f. Also, to the p-type well HPW1 of the capacitorelement CWE for writing/erasing data, 0 V is applied from each of thebit lines WBL for writing/erasing data through each of the conductorportions 7 c. As shown by the curve referred to as “Reading(Non-Selected)” and the curve referred to as “Reading (Selected)” in thegraph of FIG. 20, the coupling ratio RC2 in reading data in thenon-selected memory cell MC2 is lower than the coupling ratio RC2 inreading data in the selected memory cell MC2.

<Manufacturing Method of Semiconductor Device>

In a manufacturing method of the semiconductor device in Embodiment 2,the p⁻-type semiconductor regions 21 a are formed in a region IPP3 (seeFIG. 17) which is included in the region to be formed with the assistcapacitor element CA and into which the p-type impurity is to beimplanted in forming the p⁻-type semiconductor region 11 a in themanufacturing method of the semiconductor device in Embodiment 1. Also,in the manufacturing method of the semiconductor device in Embodiment 2,the p⁺-type semiconductor regions 21 b are formed in the region IPP3(see FIG. 17) which is included in the region to be formed with theassist capacitor element CA and into which the p-type impurity is to beimplanted in forming the p⁺-type semiconductor region 11 b in themanufacturing method of the semiconductor device in Embodiment 1. Themanufacturing method of the semiconductor device in Embodiment 2 canotherwise be the same as the manufacturing method of the semiconductordevice in Embodiment 1.

<Main Characteristic Features and Effects of Embodiment 2>

Similarly to the memory cell MC1 in the semiconductor device inEmbodiment 1, the memory cell MC2 in the semiconductor device inEmbodiment 2 includes the capacitor element CWE for writing/erasingdata, the MISFET QR for reading data, and the selection MISFET QS. Onthe other hand, unlike the memory cell MC1 in the semiconductor devicein Embodiment 1, the memory cell MC2 in the semiconductor device inEmbodiment 2 includes the assist capacitor element CA.

The assist capacitor element CA is formed in the n-type well HNW1 as theportion of the n-type well HNW which is located between the p-type wellsHPW1 and HPW2. This allows the area occupied by an area ARmc2 (see FIG.17) where one of the memory cells MC2 in Embodiment 2 is formed to beequal to the area occupied by the area ARmc1 (see FIG. 2) where one ofthe memory cells MC1 in Embodiment 1 is formed. As a result, thesemiconductor device in Embodiment 2 has effects similar to the effectsof the semiconductor device in Embodiment 1, such as the effect of,e.g., allowing a reduction in the area occupied by one of the memorycells.

Each of the memory cells MC2 in the semiconductor device in Embodiment 2further includes the assist capacitor element CA to allow the couplingratio RC1 in writing data to be set higher than in Embodiment 1. Inaddition, in writing data, it is also possible to increase the potentialdifference between the p-type well HPW1 forming the lower electrode ofthe capacitor element CWE for writing/erasing data and the capacitorelectrode FGC1 forming the upper electrode thereof. As a result, in thecapacitor element CWE, electrons are more likely to be injected as an FNtunnel current into the capacitor electrode FGC1 than in Embodiment 1.For such a reason, data can easily be written.

In the semiconductor device in Embodiment 1, when the capacitance valueCAPr is larger than the capacitance value CAPwe, in reading data, thepotential difference between the p-type well HPW2 forming the lowerelectrode of the capacitor element C serving also as the MISFET QR forreading data and the gate electrode FGR forming the upper electrodethereof cannot easily be increased.

However, in the semiconductor device in Embodiment 2, the voltageapplied to each of the p-type semiconductor regions 21 in the assistcapacitor element CA in reading data is adjusted to allow the couplingratio RC2 in reading data to be more easily increased than inEmbodiment 1. As a result, it is possible to increase the potentialdifference between the p-type well HPW2 forming the lower electrode ofthe capacitor element C serving also as the MISFET QR for reading dataand the gate electrode FGR forming the upper electrode thereof andimprove reliability in reading the data stored in the memory cell MC2.

Note that the coupling ratio RC1 in erasing data in Embodiment 2 isslightly lower than the coupling ratio RC1 in erasing data inEmbodiment 1. However, while the coupling ratio RC2 in reading data inEmbodiment 1 is less than, e.g., 0.1, the coupling ratio RC2 in readingdata in Embodiment 2 is higher than, e.g., 0.3. Accordingly, the effectof improving reliability in reading the data stored in the memory cellMC2 in Embodiment 2 is higher than in Embodiment 1.

While the invention achieved by the present inventors has beenspecifically described heretofore on the basis of the embodimentsthereof, the present invention is not limited to the foregoingembodiments. It will be appreciated that various changes andmodifications can be made in the invention within the scope notdeparting from the gist thereof.

1-17. (canceled)
 18. A semiconductor device, comprising: a semiconductorsubstrate; a first well having a first conductivity type and formed in amain surface of the semiconductor substrate; a second well having asecond conductivity type opposite to the first conductivity type andlocated so as to be included in the first well; a third well having thesecond conductivity type and located so as to be included in the firstwell and extend along the second well, while being electrically isolatedfrom the second well; and a nonvolatile memory cell located so as totwo-dimensionally overlap the second and third wells, wherein thenonvolatile memory cell includes: a floating gate electrode located soas to extend in a first direction and two-dimensionally overlap thesecond and third wells; an element for writing/erasing data located at afirst position where the floating gate electrode two-dimensionallyoverlaps the second well; and a field effect transistor for reading datalocated at a second position where the floating gate electrodetwo-dimensionally overlaps the third well, wherein the element forwriting/erasing data includes: a first electrode formed of a portion ofthe floating gate electrode which is formed at the first position; afirst insulating film formed between the first electrode and thesemiconductor substrate; a first semiconductor region and a secondsemiconductor region which are formed at respective positions in thesecond well between which the first electrode is interposed; and thesecond well, wherein the field effect transistor for reading dataincludes: a second electrode formed of a portion of the floating gateelectrode which is formed at the second position; a second insulatingfilm formed between the second electrode and the semiconductorsubstrate; and a third semiconductor region and a fourth semiconductorregion which are formed at respective positions in the third wellbetween which the second electrode is interposed, wherein the firstsemiconductor region has the first conductivity type, the secondsemiconductor region has the second conductivity type, and each of thethird and fourth semiconductor regions has the first conductivity type,wherein a length of the first electrode in a second direction crossingthe first direction is smaller than a length of the second electrode inthe second direction, wherein the nonvolatile memory cell furtherincludes a selection field effect transistor for selecting thenonvolatile memory cell, wherein the selection field effect transistorincludes: a gate electrode located so as to extend in the firstdirection and two-dimensionally overlap a portion of the third wellwhich is opposite to the second electrode relative to the fourthsemiconductor region interposed therebetween; a third insulating filmformed between the gate electrode and the semiconductor substrate; and afifth semiconductor region formed in the third well, wherein the gateelectrode is electrically isolated from the floating gate electrode,wherein the field effect transistor for reading data and the selectionfield effect transistor share the fourth semiconductor region, whereinthe fourth and fifth semiconductor regions are formed at respectivepositions in the third well between which the gate electrode isinterposed, wherein a length of the gate electrode in the seconddirection is larger than the length of the second electrode in thesecond direction, wherein a silicide layer is formed on the gateelectrode, and wherein the silicide layer is not formed on the floatinggate electrode.
 19. The semiconductor device according to claim 18,wherein an area occupied by a portion of the first electrode which isinterposed between the first and second semiconductor regions is smallerthan an area occupied by a portion of the second electrode which isinterposed between the third and fourth semiconductor regions.
 20. Thesemiconductor device according to claim 18, wherein, when a readoperation is performed to the nonvolatile memory cell, data stored inthe nonvolatile memory cell is read on the basis of a value of a currentflowing between the third and fourth semiconductor regions of the fieldeffect transistor for reading data.
 21. The semiconductor deviceaccording to claim 18, wherein the second electrode is formed of aportion of the floating gate electrode in which a length of the floatinggate electrode in the second direction is largest.
 22. The semiconductordevice according to claim 18, wherein, at any position between the firstand second positions, a length of the floating gate electrode in thesecond direction is not less than the length of the first electrode inthe second direction.
 23. The semiconductor device according to claim18, wherein, when a write operation is performed to the nonvolatilememory cell, a first voltage is applied to each of the first and thirdwells and a second voltage having a polarity opposite to a polarity ofthe first voltage is applied to the second well via the secondsemiconductor region to individually control the second and third wells,and wherein, when an erase operation is performed to the nonvolatilememory cell, a third voltage having the same polarity as the polarity ofthe first voltage is applied to the first well, the third voltage isapplied to the second well via the second semiconductor region, and afourth voltage having a polarity opposite to the polarity of the firstvoltage is applied to the third well to individually control the secondand third wells.
 24. The semiconductor device according to claim 23,wherein each of the write operation and the erase operation to thenonvolatile memory cell is performed in the element for writing/erasingdata using an FN tunnel current.
 25. The semiconductor device accordingto claim 18, wherein a width of a portion of the first electrode whichis interposed between the first and second semiconductor regions in thefirst direction is smaller than a width of a portion of the secondelectrode which is interposed between the third and fourth semiconductorregions in the first direction.